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DDR3 Differential impedance

pablo gls
Prodigy 40 points

hi,

 

what is the Differential impedance for CLK and DQS in DDR3 that is recommended by TI

it info is  missing in the DM8148 datasheet

 

regards

pablo

  • 0
    Prodigy 40 points

     

    hi ,

    is there a application note for the DDR3 layout , that add info to the DM8148 datasheet

    i want to know if there is length matching formulas for the DDR3 groups

    like example: the control to clock (minimum/maximum length), the DQS to clock (minimum/maximum length)

     

    regards

    pablo

  • 0 in reply to pablo gls
    TI__Mastermind 30110 points

    pablo gls said:

    is there a application note for the DDR3 layout , that add info to the DM8148 datasheet

    i want to know if there is length matching formulas for the DDR3 groups

    like example: the control to clock (minimum/maximum length), the DQS to clock (minimum/maximum length)

    - The only place I have seen length matching mentioned is for the "DQSn to DBn skew" specification in section 8.3.2.16.2 of SPRS614.
    It does not seem like we provide specific information on length matching related to the Clock for the other signals

    I looked as well quickly at the DM8168 DDR3 layout on the EVM (for which the layout recommendations are very close to DM8148) and it seems that length matching is done on this category of signals:
    http://support.spectrumdigital.com/boards/evm816x/reve/

    - Thanks for quoting the INTEL document (I enclosed the picture you sent below - Lane matching formulas).