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DRA78XEVM: QSPI NOR Flash reading data fail

Larry Yang
Prodigy 30 points
Part Number: DRA78XEVM
Other Parts Discussed in Thread: DRA789

The SOC part number is DRA789

NOR FLASH part number: MT25QL01GBBB

QSPI NOR Flash configurations as follows

memory map mode, 

QSPI clock is 96MHz, 

Read dummy clock cycles = 8,

Fast quad read for 3 Byte address,

read command = 6Bh,

Reading 256 Bytes data from QSPI NOR FLASH (0x602500 ~ 0x602600). There are 122 Bytes data error, always 0xFF.

Below is the waveform of QSPI-NOR flash. The first 128 Bytes data is identical to NOR FLASH, but the second 128 Bytes has error. DQ1 low level should be around 0V, but the waveform shows that it is higher than 1.5V, so the QSPI capture the input data as 0xFF. 

CH1: SCLK, CH2: DQ1, CH4: CS

  • 0
    Prodigy 30 points

    NOR FLASH part number is same as DRA78X EVM.

    Question 1:

    QSPI Pad setting is same as DRA78X EVM, Could you please check if the setting is reasonable?

    Question 2:

    About DQ1 waveform abnormal, it seems like GPMC_CSx affected the QSPI-NOR output, Could you give us any suggestion to clarify the issue is caused by SOC or NOR FLASH chip issue?

    QSPI configurations as below

  • 0
    Prodigy 30 points

    Hi Expert,

    The root cause is that QSPI-NOR running on HOLD mode when issue happened.

    The DQ3(HOLD) voltage is around 1.02V on the falling edge of CS, if HOLD pin voltage is lower than 0.99V will be judged as low level. In this case, HOLD is active.

    In order to increase the voltage margin of HOLD pin, we consider to increase the width of CS (High level)

  • 0 in reply to Larry Yang
    Prodigy 30 points

    CH1: NOR FLASH DQ3 (HOLD), CH4: NOR FLASH CS

    Hi Expert,

    Reading data from QSPI-NOR via DMA, from the image, we can see CS PIN high level width is about 90ns, if increase the width of CS, the issue can be avoided. Is it possible to modify the configuration of DRA78x QSPI to increase the width of CS? If yes, could you tell us how to do it?

    Thanks!