SK-AM62: How to change the SPI Clock from default 50Mhz

Mitesh Hiran

Part Number: SK-AM62
Other Parts Discussed in Thread: AM625, SYSCONFIG

Hello,

I am looking into adding an ADC as SPI slave and want to have AM625 SoC as SPi master. I have got the driver working but want to change the default SPI clock from 50MHZ to 1MHz or slower.

This is in the device tree but any idea how to add clk divider to generate slower clock?

main_spi0: spi@20100000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x20100000 0x00 0x400>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 141 0>;
};

The TRM says the following:

over 2 years ago

0 Mitesh Hiran over 2 years ago

Mastermind 6225 points

I have looked at the documentation but not much help.

Documentation/devicetree/bindings/spi/omap-spi.yaml

0 Mitesh Hiran over 2 years ago in reply to Mitesh Hiran

Mastermind 6225 points

root@am62xx-evm:~# dmesg | grep -i spi
[ 0.000000] GICv3: 256 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 1.099885] spi-nor: probe of spi0.0 failed with error -22
[ 1.109124] omap2_mcspi 20100000.spi: cs1 >= max 1
[ 1.113961] spi_master spi3: spi_device register error /bus@f0000/spi@2010000
0/adc@1
[ 1.121708] spi_master spi3: Failed to create SPI device for /bus@f0000/spi@2
0100000/adc@1
root@am62xx-evm:~#

0 Mitesh Hiran over 2 years ago in reply to Mitesh Hiran

Mastermind 6225 points

Removed unwanted device for cs1 from device tree and now only one error: now sure about this.

root@am62xx-evm:~# dmesg | grep -i spi
[ 0.000000] GICv3: 256 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 1.099502] spi-nor: probe of spi0.0 failed with error -22
root@am62xx-evm:~#

0 Mitesh Hiran over 2 years ago in reply to Mitesh Hiran

Mastermind 6225 points

every transfer of this

cat /sys/bus/iio/devices/iio\:device0/in_voltage0_raw
0
root@am62xx-evm:~# ^C
root@am62xx-evm:~#

I can see the clock from SPI is generated (8 clock cycles) but there is no dout or din or cs

0 Mitesh Hiran over 2 years ago in reply to Mitesh Hiran

Mastermind 6225 points

with the following settings I was able to change the clock rate.

// added for MCP320X ADCs
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <1562500>;

adc@0 {
compatible = "microchip,mcp3208";
reg = <0>;
vref-supply = <&vcc_3v3_sys>;
spi-cpha;
spi-cpol;
#io-channel-cells = <1>;
spi-max-frequency = <1500000>;
};
};

0 Mitesh Hiran over 2 years ago in reply to Mitesh Hiran

Mastermind 6225 points

Only question is why is the data out and cs from SoC (SoC is SPI Master) not driven by the SoC?

Thanks

+1 Andreas Dannenberg over 2 years ago in reply to Mitesh Hiran

TI__Guru 69707 points

Mitesh Hiran said:
clock-frequency = <1562500>;

You should not need this definition in the &main_spi0 node. The only clock frequency definitions needed are the ones in the spi device nodes, as you have it in your case within adc@0.

Mitesh Hiran said:
adc@0 {
compatible = "microchip,mcp3208";
reg = <0>;
vref-supply = <&vcc_3v3_sys>;
spi-cpha;
spi-cpol;
#io-channel-cells = <1>;
spi-max-frequency = <1500000>;
};

Can you try adding a ti,pindir-d0-out-d1-in here to see if this makes a difference.

Then, I'd suggest reviewing your pinmux definitions. You can use the SYSCONFIG tool for this, even the cloud based version, to quickly check your pinmux definitions match your hardware setup. See https://www.ti.com/tool/SYSCONFIG

Regards, Andreas

0 Mitesh Hiran over 2 years ago in reply to Andreas Dannenberg

Mastermind 6225 points

Thanks Andreas, I was about to try with 'ti,pindir-d0-out-d1-in'

but with clock-frequency = <1562500>

I see the right clock rate when I probe the clocks.

Are you saying to move that in adc@0 logic?

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SK-AM62: How to change the SPI Clock from default 50Mhz