Hi, I'm using GPEVM-AM64 and porting to examples of Hello World, hsr_mii and enet_lwip_cpsw on A53/R5_0_0/R5_1_1 respectively.
below are linker.cmd files
By using .rprc files, I made .appimage file and download to evm board.
linker.cmd of [A53 Core] ENTRY(_c_int00) __TI_STACK_SIZE = 65536; __TI_HEAP_SIZE = 131072; MEMORY { DDR : ORIGIN = 0x80000000, LENGTH = 0x2000000 /* shared memory segments */ /* On A53, * - make sure there is a MMU entry which maps below regions as non-cache */ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 } SECTIONS { .vecs : {} > DDR .text : {} > DDR .rodata : {} > DDR .data : ALIGN (8) { __data_load__ = LOADADDR (.data); __data_start__ = .; *(.data) *(.data*) . = ALIGN (8); __data_end__ = .; } > DDR /* General purpose user shared memory, used in some examples */ .bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM /* this is used when Debug log's to shared memory are enabled, else this is not used */ .bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM /* this is used only when IPC RPMessage is enabled, else this is not used */ .bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM .bss : { __bss_start__ = .; *(.bss) *(.bss.*) . = ALIGN (8); *(COMMON) __bss_end__ = .; . = ALIGN (8); } > DDR .heap (NOLOAD) : { __heap_start__ = .; KEEP(*(.heap)) . = . + __TI_HEAP_SIZE; __heap_end__ = .; } > DDR .stack (NOLOAD) : ALIGN(16) { __TI_STACK_BASE = .; KEEP(*(.stack)) . = . + __TI_STACK_SIZE; } > DDR }
linker.cmd of [R5_0_0] /* This is the stack that is used by code running within main() * In case of NORTOS, * - This means all the code outside of ISR uses this stack * In case of FreeRTOS * - This means all the code until vTaskStartScheduler() is called in main() * uses this stack. * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack */ --stack_size=32768 /* This is the heap size for malloc() API in NORTOS and FreeRTOS * This is also the heap used by pvPortMalloc in FreeRTOS */ --heap_size=65536 -e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ /* This is the size of stack when R5 is in IRQ mode * In NORTOS, * - Here interrupt nesting is enabled * - This is the stack used by ISRs registered as type IRQ * In FreeRTOS, * - Here interrupt nesting is disabled * - This is stack that is used initally when a IRQ is received * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more */ __IRQ_STACK_SIZE = 256; /* This is the size of stack when R5 is in IRQ mode * - In both NORTOS and FreeRTOS nesting is disabled for FIQ */ __FIQ_STACK_SIZE = 256; __SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ __ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ __UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ SECTIONS { /* This has the R5F entry point and vector table, this MUST be at 0x0 */ .vectors:{} palign(8) > R5F_VECS /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 * i.e this cannot be placed in DDR */ GROUP { .text.hwi: palign(8) .text.cache: palign(8) .text.mpu: palign(8) .text.boot: palign(8) .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ } > MSRAM /* This is rest of code. This can be placed in DDR if DDR is available and needed */ GROUP { .text: {} palign(8) /* This is where code resides */ .rodata: {} palign(8) /* This is where const's go */ } > MSRAM /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ GROUP { .data: {} palign(8) /* This is where initialized globals and static go */ } > MSRAM /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ GROUP { .bss: {} palign(8) /* This is where uninitialized globals go */ RUN_START(__BSS_START) RUN_END(__BSS_END) .sysmem: {} palign(8) /* This is where the malloc heap goes */ .stack: {} palign(8) /* This is where the main() stack goes */ } > MSRAM /* This is where the stacks for different R5F modes go */ GROUP { .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) RUN_START(__IRQ_STACK_START) RUN_END(__IRQ_STACK_END) .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) RUN_START(__FIQ_STACK_START) RUN_END(__FIQ_STACK_END) .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) RUN_START(__SVC_STACK_START) RUN_END(__SVC_STACK_END) .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) RUN_START(__ABORT_STACK_START) RUN_END(__ABORT_STACK_END) .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) RUN_START(__UNDEFINED_STACK_START) RUN_END(__UNDEFINED_STACK_END) } > MSRAM /* Sections needed for C++ projects */ GROUP { .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ .init_array: {} palign(8) /* Contains function pointers called before main */ .fini_array: {} palign(8) /* Contains function pointers called after main */ } > MSRAM /* Packet buffer memory used by ICCS */ .bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM /* General purpose user shared memory, used in some examples */ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM /* this is used when Debug log's to shared memory are enabled, else this is not used */ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM /* this is used only when IPC RPMessage is enabled, else this is not used */ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM /* General purpose non cacheable memory, used in some examples */ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM } /* NOTE: Below memory is reserved for DMSC usage - During Boot till security handoff is complete 0x701E0000 - 0x701FFFFF (128KB) - After "Security Handoff" is complete (i.e at run time) 0x701F4000 - 0x701FFFFF (48KB) Security handoff is complete when this message is sent to the DMSC, TISCI_MSG_SEC_HANDOVER This should be sent once all cores are loaded and all application specific firewall calls are setup. */ MEMORY { R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 /* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */ ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000 /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 /* when using multi-core application's i.e more than one R5F/M4F active, make sure * this memory does not overlap with other R5F's */ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x00120000 /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable */ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 /* shared memory segments */ /* On R5F, * - make sure there is a MPU entry which maps below regions as non-cache */ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 }
linker cmd of [R5_1_1] #include "ti_enet_config.h" /* This is the stack that is used by code running within main() * In case of NORTOS, * - This means all the code outside of ISR uses this stack * In case of FreeRTOS * - This means all the code until vTaskStartScheduler() is called in main() * uses this stack. * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack */ --stack_size=8192 /* This is the heap size for malloc() API in NORTOS and FreeRTOS * This is also the heap used by pvPortMalloc in FreeRTOS */ --heap_size=34000 -e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ /* This is the size of stack when R5 is in IRQ mode * In NORTOS, * - Here interrupt nesting is disabled as of now * - This is the stack used by ISRs registered as type IRQ * In FreeRTOS, * - Here interrupt nesting is enabled * - This is stack that is used initally when a IRQ is received * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more */ __IRQ_STACK_SIZE = 256; /* This is the size of stack when R5 is in IRQ mode * - In both NORTOS and FreeRTOS nesting is disabled for FIQ */ __FIQ_STACK_SIZE = 256; __SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ __ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ __UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ SECTIONS { /* This has the R5F entry point and vector table, this MUST be at 0x0 */ .vectors:{} palign(8) > R5F_VECS /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 * i.e this cannot be placed in DDR */ GROUP { .text.hwi: palign(8) .text.cache: palign(8) .text.mpu: palign(8) .text.boot: palign(8) .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ } > MSRAM /* This is rest of code. This can be placed in DDR if DDR is available and needed */ GROUP { .text: {} palign(8) /* This is where code resides */ .rodata: {} palign(8) /* This is where const's go */ } > DDR /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ GROUP { .data: {} palign(8) /* This is where initialized globals and static go */ } > DDR /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ GROUP { .sysmem: {} palign(8) /* This is where the malloc heap goes */ .stack: {} palign(8) /* This is where the main() stack goes */ } > DDR GROUP { .bss: {} palign(8) /* This is where uninitialized globals go */ RUN_START(__BSS_START) RUN_END(__BSS_END) } > DDR /* This is where the stacks for different R5F modes go */ GROUP { .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) RUN_START(__IRQ_STACK_START) RUN_END(__IRQ_STACK_END) .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) RUN_START(__FIQ_STACK_START) RUN_END(__FIQ_STACK_END) .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) RUN_START(__SVC_STACK_START) RUN_END(__SVC_STACK_END) .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) RUN_START(__ABORT_STACK_START) RUN_END(__ABORT_STACK_END) .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) RUN_START(__UNDEFINED_STACK_START) RUN_END(__UNDEFINED_STACK_END) } > DDR /* General purpose user shared memory, used in some examples */ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM /* this is used when Debug log's to shared memory are enabled, else this is not used */ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM /* this is used only when IPC RPMessage is enabled, else this is not used */ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM .enet_dma_mem { *(*ENET_DMA_DESC_MEMPOOL) *(*ENET_DMA_RING_MEMPOOL) #if (ENET_SYSCFG_PKT_POOL_ENABLE == 1) *(*ENET_DMA_PKT_MEMPOOL) #endif } (NOLOAD) {} ALIGN (128) > DDR .bss:ENET_DMA_OBJ_MEM (NOLOAD) {} ALIGN (128) > MSRAM .bss:ENET_DMA_PKT_INFO_MEMPOOL (NOLOAD) {} ALIGN (128) > MSRAM .bss:ENET_ICSSG_OCMC_MEM (NOLOAD) {} ALIGN (128) > MSRAM } /* NOTE: Below memory is reserved for DMSC usage - During Boot till security handoff is complete 0x701E0000 - 0x701FFFFF (128KB) - After "Security Handoff" is complete (i.e at run time) 0x701FC000 - 0x701FFFFF (16KB) Security handoff is complete when this message is sent to the DMSC, TISCI_MSG_SEC_HANDOVER This should be sent once all cores are loaded and all application specific firewall calls are setup. */ MEMORY { R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 /* when using multi-core application's i.e more than one R5F/M4F active, make sure * this memory does not overlap with other R5F's */ MSRAM : ORIGIN = 0x70140000 , LENGTH = 0x40000 /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable */ FLASH : ORIGIN = 0x60180000 , LENGTH = 0x80000 /* when using multi-core application's i.e more than one R5F/M4F active, make sure * this memory does not overlap with other R5F's */ DDR : ORIGIN = 0x82000000 , LENGTH = 0x20000000 /* shared memory segments */ /* On R5F, * - make sure there is a MPU entry which maps below regions as non-cache */ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 }
As a result, Hello world(A53) and cpsw example is working as I expected. But hsr_mii example is not work well.
on terminal console, it displayed from "Initialized PRP module" to "Mode: MII"
How to solve this problem.