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AM6442: uboot code hanging because of GPMC register access

Part Number: AM6442


Hello,

I have an issue with GPMC peripheral during boot process of AM6442 chip.

Short description of issue: In certain conditions, the u-boot code is hanging when I try to read a GPMC register (for example reg GPMC_REVISION).

Long description:

My setup is the following: AM6442 chip on a custom board, with boot from NAND (and initial tiboot3.bin boot file either on NAND or on SD card, I am testing both cases).

I am using this TI U-Boot version "ti-u-boot-08.06.00.007".

When fully booting from NAND, I have the following behavior:

  • 1st call to U-Boot (running on R5F) --> no issues, boot is happening properly (including all accesses to GPMC registers)
  • 2nd call to U-Boot (running on A53) --> the code is hanging after the first access to a GPMC register (in the initial code this is the GPMC_CONFIG7_0 register, and if I modify the code to first access GPMC_REVISION register, I have the same behavior)

When first booting on SD card and then switching to NAND and after initial R5F init, I have the following behavior:

  • 1st call to U-Boot (running on R5F) --> no issues, boot is happening properly (including all accesses to GPMC registers)
  • 2nd call to U-Boot (running on A53) --> no issues, boot is happening properly (including all accesses to GPMC registers).
  • After that I have a 3rd call to U-Boot and finally the kernel is starting.

 

Can help me figure what is happening and find a way to solve that issue?

  • I checked the status of the GPMC peripheral and associated clocks, everything seems to be ON in all cases (looking at ti calls dev_ops->is_on() and clk_ops->is_on()).
  • When the code hangs, there is no error message, this doesn't look like a C code crash. A printf added just before a call to readl_relaxed(gpmc_base + xxx) is working properly but any code added after readl_relaxed() is not called.
  • I cannot figure what is happening differently in the case I first run from SD... By the time U-Boot runs on A53, U-Boot code is in NAND in both cases.

Best regards,

Stephane

  • Hello,

    Nobody has any clue of what can happen? On my side I'm trying to modify the JTAG circuit of the custom board so that I have access to it and get a better view of the chip state when the code is hanging.

    With the code, is there anything else i can look at? Right now I'm using this code:

    #include <linux/soc/ti/ti_sci_protocol.h>
    
    bool req_state;
    bool current_state;
    struct ti_sci_handle *ti_sci = get_ti_sci_handle();
    struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
    struct ti_sci_clk_ops *clk_ops = &ti_sci->ops.clk_ops;
    
    // check if device is activated
    ret = dev_ops->is_on(ti_sci, TISCI_AM64X_DEV_GPMC0, &req_state, &current_state);
    
    // check if all clocks are activated
    for (ii=0; ii<5; ii++)
    {
    	ret = clk_ops->is_on(ti_sci, TISCI_AM64X_DEV_GPMC0, ii, &req_state, &current_state);
    }

    • For the device check, req_state = 1, current_state = 1.
    • For all clock checks, req_state = 0, current_state = 1.

    Is there another way to see what could be wrong with the GPMC peripheral?

    Best regards,

    Stephane

  • Hello,

    Please allow a few days to look into this issue. My apologies for the delay.

  • Hello Stephane,
    I tested u-boot NAND flashing/booting using AM64x SDK 8.2 on AM64x GP EVM + TI NAND daughter card.
    u-boot NAND boot worked for your reference
    e2e.ti.com/.../4072372
    Best,
    -Hong

  • Hello Hong,

    Thanks for the reply. It gives me hope that it can work, but I have no clue how to find the issue on my setup... Maybe I will try to reproduce what you did with the AM64x SDK 8.2. I already have the GP EVM in my possession, can you please give the reference of the TI NAND daughter card you used? I will try to order it and start comparing your setup with mine.

    Best regards,

    Stephane

  • Hello Stephane,
    It turns out that the GPMC-NAND daughter card is for TI internal use only, not orderable by customers.
    I'm attaching the GPMC-NAND daughter card schematic here for your reference, and hopefully it is helpful to you.
    Best,
    -Hong

    PROC121E1(001)_SCH.pdf

  • Hello,

    Thanks for the schematics. If you used a 3rd party for the board routing and assembly, it is possible to know who it was? It would facilitate my task if I can just order this prototype board to this 3rd party. Like this I would be able to compare your setup and mine in just a couple of weeks (supposing there is no shortage of components, which is another story...).

    In the meantime, about the main issue I am facing, what could be the root cause for a code crash when reading an internal register for the GPMC peripheral on the AM6442 chip? Is there anything else other than the missing clock hypothesis? 

    Best regards,

    Stephane 

  • Hello Stephane,
    Regarding GPMC accessbility, there's one early e2e for your reference on your current issue.
    e2e.ti.com/.../3902365

    On the internal NAND daughter card, I'm checking my colleague in HW/EVM team to see any options...
    Best,
    -Hong

  • Hi,

    If not possible to order the TDMS64DC02EVM board, can you instead give me the full design package of that board? Usually TI provides a zip with the BOM (.xlsx), the pcb details (.brd and .dsn) on top of the schematics (.pdf). For example https://www.ti.com/lit/zip/swrr171 for the TMDS64GPEVM board.

    Thanks,

    Stephane

  • Hello Stephane,
    I checked my colleague in HW/EVM team, and one option is sharing the NAND daughter-card design package with you via email.
    Best,
    -Hong

  • Hello Stephane,

    I've invited you to view these files on our 3rd party file sharing service. Look out for an email sent to above email address.

    Regards,
    Mark

  • Hi Stephane,
    Thanks for your offline email, and good to know you received the HW design file package.
    I’ll move the e2e to resolved for now.
    Please post any follow-up questions to a new e2e.
    Best,
    -Hong

  • Hi Hong,

    Before we close this thread, I have 2 follow-up questions about the NAND daughter board and the test you did last year:

    • Which information do I need to write in the daughter board EEPROM for the EVM to properly recognize it?
    • Do I need to change any TI U-Boot source file (.dts, config,...) for U-Boot to properly recognize the NAND chip and boot from it? Or are all modifications already present in the U-Boot files given in the SDK?

    Regards,

    Stephane

  • Hi Hong,

    I finally managed to have the NAND boot working with U-Boot 08.02 on my custom board. But when I switch to U-Boot version 08.06, the NAND boot stops working, I observe that the code is hanging after the GPMC register access. At the same time, the SD boot is working fine with both 08.02 and 08.06. 

    So I'm fearing that the issue comes from changes coming from U-Boot files, not from changes done on my side. Did you test the NAND boot on your side with U-Boot version 08.06? The post you referenced showed tests done last year on 08.02.

    Best regards,

    Stephane

  • Hi Stephane,
    Thanks for the update, and it is good to know NAND booting works on your board with your SW ported from u-boot 8.2.
    I'll check u-boot 8.6 on my setup next week, and keep you posted.
    Best,
    -Hong

  • Hello Hong,

    Did you have a chance to test with u-boot 8.6?

    Best regards,

    Stephane

  • Hi Stephane,
    I was out of office last few days, and haven't tested GPMC-NAND boot on AM64x GP EVM + daughtercard with SDK8.6 yet.
    I'll try it out this week, and keep you posted.
    Best,
    -Hong

  • Hi Stephane,
    I reproduced the u-boot GPMC-NAND booting issue with SDK 8.6 on AM64x EVM + NAND daughter card.
    As a temprory WA, reverting this commit ID
    git.ti.com/.../
    I'm attaching two logs after reverting the above commit ID
    - am64_8.6_patch_nand_flash.log: nand flashing
    - am64_8.6_patch_nand_boot.log: nand booting
    Best,
    -Hong

    U-Boot SPL 2021.01-g2ee8efd654 (Feb 23 2023 - 22:21:41 +0000)
    Resetting on cold boot to workaround ErrataID:i2331
    resetting ...
    
    U-Boot SPL 2021.01-g2ee8efd654 (Feb 23 2023 - 22:21:41 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    SPL initial stack usage: 13424 bytes
    Detected: TMDS64DC02EVM rev E1
    Trying to boot from NAND
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    init_env from device 11 not supported!
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
    NOTICE:  BL31: Built : 15:41:21, Jan 24 2023
    I/TC: 
    I/TC: OP-TEE version: 3.20.0 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Tue Feb 21 18:20:15 UTC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    I/TC: Primary CPU switching to normal world boot
    
    U-Boot SPL 2021.01-g2ee8efd654 (Feb 23 2023 - 22:21:31 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    Detected: TMDS64DC02EVM rev E1
    Trying to boot from NAND
    
    U-Boot SPL 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:23:05 -0500)
    Resetting on cold boot to workaround ErrataID:i2331
    resetting ...
    
    U-Boot SPL 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:23:05 -0500)
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    SPL initial stack usage: 13432 bytes
    Detected: TMDS64DC02EVM rev E1
    Trying to boot from MMC2
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
    NOTICE:  BL31: Built : 13:45:56, Feb 27 2023
    I/TC: 
    I/TC: OP-TEE version: 3.20.0 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Mon Feb 27 13:46:53 UTC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    I/TC: Primary CPU switching to normal world boot
    
    U-Boot SPL 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:22:29 -0500)
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    Detected: TMDS64DC02EVM rev E1
    Trying to boot from MMC2
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    
    
    U-Boot 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:22:29 -0500)
    
    SoC:   AM64X SR2.0 GP
    Model: Texas Instruments AM642 EVM
    Board: AM64-GPEVM rev E2
    DRAM:  2 GiB
    NAND:  1024 MiB
    MMC:   mmc@fa10000: 0, mmc@fa00000: 1
    Loading Environment from FAT... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Detected: TMDS64DC02EVM rev E1
    Net:   eth0: ethernet@8000000port@1
    Hit any key to stop autoboot:  2  0 
    => md.l 0x43000030 1
    43000030: 00000243                               C...
    => nand erase.chip
    
    NAND erase.chip: device 0 whole chip
    
    Erasing at 0x0 --   0% complete.
    Erasing at 0xa00000 --   1% complete.
    Erasing at 0x1440000 --   2% complete.
    Erasing at 0x1e80000 --   3% complete.
    Erasing at 0x28c0000 --   4% complete.
    Erasing at 0x3300000 --   5% complete.
    Erasing at 0x3d40000 --   6% complete.
    Erasing at 0x4780000 --   7% complete.
    Erasing at 0x51c0000 --   8% complete.
    Erasing at 0x5c00000 --   9% complete.
    Erasing at 0x6640000 --  10% complete.
    Erasing at 0x7080000 --  11% complete.
    Erasing at 0x7ac0000 --  12% complete.
    Erasing at 0x8500000 --  13% complete.
    Erasing at 0x8f40000 --  14% complete.
    Erasing at 0x9980000 --  15% complete.
    Erasing at 0xa3c0000 --  16% complete.
    Erasing at 0xae00000 --  17% complete.
    Erasing at 0xb840000 --  18% complete.
    Erasing at 0xc280000 --  19% complete.
    Erasing at 0xccc0000 --  20% complete.
    Erasing at 0xd700000 --  21% complete.
    Erasing at 0xe140000 --  22% complete.
    Erasing at 0xeb80000 --  23% complete.
    Erasing at 0xf5c0000 --  24% complete.
    Erasing at 0xffc0000 --  25% complete.
    Erasing at 0x10a00000 --  26% complete.
    Erasing at 0x11440000 --  27% complete.
    Erasing at 0x11e80000 --  28% complete.
    Erasing at 0x128c0000 --  29% complete.
    Erasing at 0x13300000 --  30% complete.
    Erasing at 0x13d40000 --  31% complete.
    Erasing at 0x14780000 --  32% complete.
    Erasing at 0x151c0000 --  33% complete.
    Erasing at 0x15c00000 --  34% complete.
    Erasing at 0x16640000 --  35% complete.
    Erasing at 0x17080000 --  36% complete.
    Erasing at 0x17ac0000 --  37% complete.
    Erasing at 0x18500000 --  38% complete.
    Erasing at 0x18f40000 --  39% complete.
    Erasing at 0x19980000 --  40% complete.
    Erasing at 0x1a3c0000 --  41% complete.
    Erasing at 0x1ae00000 --  42% complete.
    Erasing at 0x1b840000 --  43% complete.
    Erasing at 0x1c280000 --  44% complete.
    Erasing at 0x1ccc0000 --  45% complete.
    Erasing at 0x1d700000 --  46% complete.
    Erasing at 0x1e140000 --  47% complete.
    Erasing at 0x1eb80000 --  48% complete.
    Erasing at 0x1f5c0000 --  49% complete.
    Erasing at 0x1ffc0000 --  50% complete.
    Erasing at 0x20a00000 --  51% complete.
    Erasing at 0x21440000 --  52% complete.
    Erasing at 0x21e80000 --  53% complete.
    Erasing at 0x228c0000 --  54% complete.
    Erasing at 0x23300000 --  55% complete.
    Erasing at 0x23d40000 --  56% complete.
    Erasing at 0x24780000 --  57% complete.
    Erasing at 0x251c0000 --  58% complete.
    Erasing at 0x25c00000 --  59% complete.
    Erasing at 0x26640000 --  60% complete.
    Erasing at 0x27080000 --  61% complete.
    Erasing at 0x27ac0000 --  62% complete.
    Erasing at 0x28500000 --  63% complete.
    Erasing at 0x28f40000 --  64% complete.
    Erasing at 0x29980000 --  65% complete.
    Erasing at 0x2a3c0000 --  66% complete.
    Erasing at 0x2ae00000 --  67% complete.
    Erasing at 0x2b840000 --  68% complete.
    Erasing at 0x2c280000 --  69% complete.
    Erasing at 0x2ccc0000 --  70% complete.
    Erasing at 0x2d700000 --  71% complete.
    Erasing at 0x2e140000 --  72% complete.
    Erasing at 0x2eb80000 --  73% complete.
    Erasing at 0x2f5c0000 --  74% complete.
    Erasing at 0x2ffc0000 --  75% complete.
    Erasing at 0x30a00000 --  76% complete.
    Erasing at 0x31440000 --  77% complete.
    Erasing at 0x31e80000 --  78% complete.
    Erasing at 0x328c0000 --  79% complete.
    Erasing at 0x33300000 --  80% complete.
    Erasing at 0x33d40000 --  81% complete.
    Erasing at 0x34780000 --  82% complete.
    Erasing at 0x351c0000 --  83% complete.
    Erasing at 0x35c00000 --  84% complete.
    Erasing at 0x36640000 --  85% complete.
    Erasing at 0x37080000 --  86% complete.
    Erasing at 0x37ac0000 --  87% complete.
    Erasing at 0x38500000 --  88% complete.
    Erasing at 0x38f40000 --  89% complete.
    Erasing at 0x39980000 --  90% complete.
    Erasing at 0x3a3c0000 --  91% complete.
    Erasing at 0x3ae00000 --  92% complete.
    Erasing at 0x3b840000 --  93% complete.
    Erasing at 0x3c280000 --  94% complete.
    Erasing at 0x3ccc0000 --  95% complete.
    Erasing at 0x3d700000 --  96% complete.
    Erasing at 0x3e140000 --  97% complete.
    Erasing at 0x3eb80000 --  98% complete.
    Erasing at 0x3f5c0000 --  99% complete.
    Erasing at 0x3ffc0000 -- 100% complete.
    OK
    => load mmc 1 ${loadaddr} tiboot3.bin
    574531 bytes read in 27 ms (20.3 MiB/s)
    => nand write ${loadaddr} 0x0 ${filesize}
    
    NAND write: device 0 offset 0x0, size 0x8c443
     574531 bytes written: OK
    => load mmc 1 ${loadaddr} tispl.bin
    902143 bytes read in 41 ms (21 MiB/s)
    => nand write ${loadaddr} 0x200000 ${filesize}
    
    NAND write: device 0 offset 0x200000, size 0xdc3ff
     902143 bytes written: OK
    => load mmc 1 ${loadaddr} u-boot.img
    1131471 bytes read in 50 ms (21.6 MiB/s)
    => nand write ${loadaddr} 0x600000 ${filesize}
    
    NAND write: device 0 offset 0x600000, size 0x1143cf
     1131471 bytes written: OK
    => 

    U-Boot SPL 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:23:05 -0500)
    Resetting on cold boot to workaround ErrataID:i2331
    resetting ...
    
    U-Boot SPL 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:23:05 -0500)
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    SPL initial stack usage: 13432 bytes
    Detected: TMDS64DC02EVM rev E1
    Trying to boot from NAND
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    init_env from device 11 not supported!
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
    NOTICE:  BL31: Built : 13:45:56, Feb 27 2023
    I/TC: 
    I/TC: OP-TEE version: 3.20.0 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Mon Feb 27 13:46:53 UTC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    I/TC: Primary CPU switching to normal world boot
    
    U-Boot SPL 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:22:29 -0500)
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
    Detected: TMDS64DC02EVM rev E1
    Trying to boot from NAND
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    
    
    U-Boot 2021.01-00002-g82410ee-dirty (Jul 11 2023 - 11:22:29 -0500)
    
    SoC:   AM64X SR2.0 GP
    Model: Texas Instruments AM642 EVM
    Board: AM64-GPEVM rev E2
    DRAM:  2 GiB
    NAND:  1024 MiB
    MMC:   mmc@fa10000: 0, mmc@fa00000: 1
    Loading Environment from FAT... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Detected: TMDS64DC02EVM rev E1
    Net:   eth0: ethernet@8000000port@1
    Hit any key to stop autoboot:  2  0 
    => md.l 0x43000030 1
    43000030: 0000025b                               [...
    => 

  • Thank you Hong for confirming the issue and proposing the workaround, I will try the same fix on my board and let you know.

  • Hi Stephane,
    yes, please keep us posted once you have chance running test on your customer board.
    Best,
    -Hong

  • Hello Hong,

    I reverted the commit you pointed to me on 08.06, and the boot worked fine. Thank you very much!

    Do you know what will be the timeline for a proper release of the issue fix? In the meantime, I will mark this post as resolved, the workaround allows me to not be blocked anymore.

    Best regards,

    Stephane