TDA2SX: related issue

/*
* ======== mem_segment_definition.xs ========
* ======== Single file for the memory map configuration of all cores =========
*/

function getMemSegmentDefinition_external(core)
{
KB=1024;
MB=KB*KB;

DDR3_ADDR = 0x80000000;
DDR3_SIZE = 512*MB;

/*
* In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1
* are hard-coded in as values of gIpcNonCachedDataAddr and
* gIpcNonCachedDataSize in Ipu1_0.cfg
* If this DDR3_BASE_SIZE_0 is changed, update Ipu1_0.cfg
*/
DDR3_BASE_ADDR_0 = DDR3_ADDR;
DDR3_BASE_SIZE_0 = 507*MB;

/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
* to map SR0, REMOTE_LOG_MEM sections.
* tlb_config_eveX.c need to be modified otherwise
*/
DDR3_BASE_ADDR_1 = DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0;
DDR3_BASE_SIZE_1 = DDR3_SIZE - DDR3_BASE_SIZE_0;
//if(core=="ipu1_1" || core=="ipu1_0" || core=="ipu2" || core=="a15_0")
//{
/* for ipu1_0, ipu1_1, ipu2 DDR3_BASE_ADDR_1 should be
* in non-cached virtual address of
* DDR3_BASE_ADDR_1 + 512*MB
*/
DDR3_BASE_ADDR_1 = DDR3_BASE_ADDR_1+512*MB;
//}

DSP1_L2_SRAM_ADDR = 0x40800000;
DSP1_L2_SRAM_SIZE = 288*KB;

DSP2_L2_SRAM_ADDR = 0x41000000;
DSP2_L2_SRAM_SIZE = 288*KB;

EVE1_SRAM_ADDR = 0x42000000;
EVE1_SRAM_SIZE = 1*MB;

EVE2_SRAM_ADDR = 0x42100000;
EVE2_SRAM_SIZE = 1*MB;

EVE3_SRAM_ADDR = 0x42200000;
EVE3_SRAM_SIZE = 1*MB;

EVE4_SRAM_ADDR = 0x42300000;
EVE4_SRAM_SIZE = 1*MB;

TOTAL_MEM_SIZE = (DDR3_SIZE);

/* First 512 MB - cached */
/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
* the entire vecs+code+data in 16MB section. In this case a single TLB map would
* be enough to map vecs+code+data of an EVE.
* tlb_config_eveX.c need to be modified if any of these EVE memory sections or
* SR1_FRAME_BUFFER_MEM section is modified.
*/

/* EVE self-branch instruction block - EVE1_VECS
* In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
* This could overwrites the code/data loaded at 0x80000000.
* So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
* EVE self-branch instruction if no AppImage for EVE.
* If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
* and hence we did not observe any issue.
* If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
* if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
*/

EVE1_VECS_SIZE = 0.5*MB;
EVE1_CODE_SIZE = 2*MB;
EVE1_DATA_SIZE =13.5*MB;
EVE2_VECS_SIZE = 0.5*MB;
EVE2_CODE_SIZE = 2*MB;
EVE2_DATA_SIZE =13.5*MB;
EVE3_VECS_SIZE = 0.5*MB;
EVE3_CODE_SIZE = 2*MB;
EVE3_DATA_SIZE =13.5*MB;
EVE4_VECS_SIZE = 0.5*MB;
EVE4_CODE_SIZE = 2*MB;
EVE4_DATA_SIZE =13.5*MB;
NDK_DATA_SIZE = 8*MB;

if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes")
{
IPU1_1_CODE_SIZE = 2.5*MB;
IPU1_1_DATA_SIZE = 12.5*MB;
IPU1_0_CODE_SIZE = 6*MB;
IPU1_0_DATA_SIZE = 12*MB;
}
else
{
IPU1_1_CODE_SIZE = 2.5*MB;
IPU1_1_DATA_SIZE = 12.5*MB;
IPU1_0_CODE_SIZE = 6*MB;
IPU1_0_DATA_SIZE = 16*MB;
}
IPU2_CODE_SIZE = 2*MB;
IPU2_DATA_SIZE = 7*MB;
DSP1_CODE_SIZE = 6*MB;
DSP1_DATA_SIZE = 14*MB;
DSP1_DATA_SIZE_2 = 1*MB;
DSP2_CODE_SIZE = 4*MB;
DSP2_DATA_SIZE = 14*MB;
DSP2_DATA_SIZE_2 = 1*MB;
/* A15_0_CODE_SIZE reduced since it is not used in .bld file.
* Check .bld for details. Originally 2 + 14 MB.
*/
A15_0_DATA_SIZE = 43.5*MB;
if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
{
A15_0_DATA_SIZE_INC = 101*MB /* in MB */
A15_0_DATA_SIZE = (A15_0_DATA_SIZE + A15_0_DATA_SIZE_INC);
}

if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes")
{
/* Ensure ECC regions are 64kB aligned */
SR1_FRAME_BUFFER_SIZE = 297.5*MB;
SR1_BUFF_ECC_ASIL_SIZE = 1*MB;
SR1_BUFF_ECC_QM_SIZE = 40*MB;
SR1_BUFF_NON_ECC_ASIL_SIZE = 1*MB;
}
else
{
SR1_BUFF_ECC_ASIL_SIZE = 4*KB;
SR1_BUFF_ECC_QM_SIZE = 4*KB;
SR1_BUFF_NON_ECC_ASIL_SIZE = 4*KB;
SR1_FRAME_BUFFER_SIZE = 305.5*MB - (SR1_BUFF_ECC_ASIL_SIZE + SR1_BUFF_ECC_QM_SIZE + SR1_BUFF_NON_ECC_ASIL_SIZE);
if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
{
SR1_FRAME_BUFFER_SIZE = SR1_FRAME_BUFFER_SIZE - A15_0_DATA_SIZE_INC;
}
}

/* Second 512 MB - non-cached */
/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
* to map SR0, REMOTE_LOG_MEM sections.
* tlb_config_eveX.c need to be modified otherwise
*/
REMOTE_LOG_SIZE = 160*KB;
SYSTEM_IPC_SHM_SIZE = 480*KB;
SYSTEM_AUTOSAR_IPC_SHM_SIZE = 512*KB;
LINK_STATS_SIZE = 256*KB;
HDVPSS_DESC_SIZE = 1024*KB;
SR0_SIZE = 128*KB;
OPENVX_SHM_SIZE = 1984*KB;
EEPROM_PARAM_SIZE = 64*KB;

if((java.lang.System.getenv("OPENCL_INCLUDE") == "yes"))
{
/* when OpenCL is enabled we need more SR0 space
*/
SR0_SIZE = 2*MB;
}