I have a problem in interfacing tms320vc5502 with hynix SDRAM HY57V161610D-10I which is 2bank*512k*16bit. The SDRAM connects to CE3. I am not capable of modifying the data in the memory window of CCS, which indicates DSP fails to write the SDRAM. In order to test the timing sequence of write, I keeps writing to the SDRAM. From what i observed, SDCAS can be pulled low with the CE3 . However, SDRAS keeps high except the case of auto reflesh of the SDRAM. I didn't see the ACTV signal. I have configured the EMIF register below. What could the problem be if SDRAS can not be pulled low? Thanks.
EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK( // EMIF Global Control Register 1
EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED, // Hold enable
EMIF_GBLCTL1_EK1HZ_EK1EN, // High-Z control
EMIF_GBLCTL1_EK1EN_ENABLED // ECLKOUT1 Enable
),
EMIF_GBLCTL2_RMK( // EMIF Global Control Register 2
EMIF_GBLCTL2_EK2RATE_1XCLK, // ECLKOUT2 Rate
EMIF_GBLCTL2_EK2HZ_EK2EN, // EK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
EMIF_GBLCTL2_EK2EN_ENABLED // ECLKOUT2 Enable (enabled by default)
),
EMIF_CE1CTL1_RMK( // CE1 Space Control Register 1
EMIF_CE1CTL1_TA_OF(3), // Turn-Around time
EMIF_CE1CTL1_READ_STROBE_OF(6), // Read strobe width
EMIF_CE1CTL1_MTYPE_16BIT_ASYNC, // Access type
EMIF_CE1CTL1_WRITE_HOLD_MSB_LOW, // Write hold width MSB bitHIGH
EMIF_CE1CTL1_READ_HOLD_OF(3) // Read hold width
),
EMIF_CE1CTL2_RMK( // CE1 Space Control Register 2
EMIF_CE1CTL2_WRITE_SETUP_OF(4), // Write setup width
EMIF_CE1CTL2_WRITE_STROBE_OF(10), // Write strobe width
EMIF_CE1CTL2_WRITE_HOLD_OF(2), // Write hold width
EMIF_CE1CTL2_READ_SETUP_OF(2) // Read setup width
),
EMIF_CE0CTL1_RMK( // CE0 Space Control Register 1
EMIF_CE0CTL1_TA_DEFAULT,
EMIF_CE0CTL1_READ_STROBE_OF(5), //5
EMIF_CE0CTL1_MTYPE_16BIT_ASYNC,
EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE0CTL1_READ_HOLD_OF(1)
),
EMIF_CE0CTL2_RMK( // CE0 Space Control Register 2
EMIF_CE0CTL2_WRITE_SETUP_OF(1),
EMIF_CE0CTL2_WRITE_STROBE_OF(2),
EMIF_CE0CTL2_WRITE_HOLD_OF(1),
EMIF_CE0CTL2_READ_SETUP_OF(1)
),
EMIF_CE2CTL1_RMK( // CE2 Space Control Register 1, for USB
EMIF_CE2CTL1_TA_DEFAULT,
EMIF_CE2CTL1_READ_STROBE_OF(3),
EMIF_CE2CTL1_MTYPE_32BIT_ASYNC, // assumed as 32-bit-wide memory
EMIF_CE2CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE2CTL1_READ_HOLD_OF(3)
),
EMIF_CE2CTL2_RMK( // CE2 Space Control Register 2
EMIF_CE2CTL2_WRITE_SETUP_OF(3),
EMIF_CE2CTL2_WRITE_STROBE_OF(3),
EMIF_CE2CTL2_WRITE_HOLD_OF(3),
EMIF_CE2CTL2_READ_SETUP_OF(3)
),
EMIF_CE3CTL1_RMK( // CE3 Space Control Register 1
EMIF_CE3CTL1_TA_DEFAULT,
EMIF_CE3CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_16BIT_SDRAM, // 16-bit-wide SDRAM
EMIF_CE3CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE3CTL2_RMK( // CE3 Space Control Register 2
EMIF_CE3CTL2_WRITE_SETUP_DEFAULT, // Write setup width
EMIF_CE3CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
EMIF_CE3CTL2_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_SDCTL1_RMK( // SDRAM Control Register 1
EMIF_SDCTL1_TRC_OF(6), // Specifies tRC value of the SDRAM in EMIF clock cycles.
EMIF_SDCTL1_SLFRFR_DISABLED // Auto-refresh mode
),
EMIF_SDCTL2_RMK( // SDRAM Control Register 2
0x01, // 2 banks,11 row address, 8 column address
EMIF_SDCTL2_RFEN_ENABLED, // Refresh enabled
EMIF_SDCTL2_INIT_INIT_SDRAM,
EMIF_SDCTL2_TRCD_OF(1),
EMIF_SDCTL2_TRP_OF(1)
),
0x05DC, // SDRAM Refresh Control Register 1
0x0300, // SDRAM Refresh Control Register 2
EMIF_SDEXT1_RMK( // SDRAM Extension Register 1
EMIF_SDEXT1_R2WDQM_2CYCLES,
EMIF_SDEXT1_RD2WR_4CYCLES,
EMIF_SDEXT1_RD2DEAC_1CYCLE,
EMIF_SDEXT1_RD2RD_1CYCLE,
EMIF_SDEXT1_THZP_OF(2),
EMIF_SDEXT1_TWR_OF(0),
EMIF_SDEXT1_TRRD_2CYCLES,
EMIF_SDEXT1_TRAS_OF(4),
EMIF_SDEXT1_TCL_3CYCLES
),
EMIF_SDEXT2_RMK( // SDRAM Extension Register 2
EMIF_SDEXT2_WR2RD_0CYCLES,
EMIF_SDEXT2_WR2DEAC_1CYCLE,
0,
EMIF_SDEXT2_R2WDQM_2CYCLES
),
EMIF_CE1SEC1_DEFAULT, // CE1 Secondary Control Register 1
EMIF_CE0SEC1_DEFAULT, // CE0 Secondary Control Register 1
EMIF_CE2SEC1_DEFAULT, // CE2 Secondary Control Register 1
EMIF_CE3SEC1_DEFAULT, // CE3 Secondary Control Register 1
EMIF_CESCR_DEFAULT // CE Size Control Register
};
