AM6442: GPMC WAIT signal

Hello Hideaki,

Thank you for the query.

Hideaki Matsumoto said:

They are considering the memory connection configuration, and would like to confirm whether the parallel bus can be made into a multi-master configuration. Is it possible ?

Please refer 

12.3.3.2.2 GPMC I/O Signals

Looks like the GPMC as the name implies works only as a controller (master).

I am checking internally on the other query.

Regards,

Sreenivasa

Hi Hideaki-san,

By setting WAITWRITEMONITORING or WAITREADMONITORING in GPMC_CONFIG1_i, the asserted WAIT pin will not delay the start of an access request, but it will delay the access time (or timeout waiting for WAIT to be released). WAIT is monitored just before RDACCESSTIME or WRACCESSTIME of a access cycle. Refer to AM64x TRM

section 12.3.3.4.7.3.1 WAIT Pin Monitoring Control.

However, before beginning an access request software can poll the WAITxSTATUS bit of the GPMC_STATUS register which indicates the WAIT status state (where x = 0 to 1).

Or software can respond to an interrupt on a WAIT pin edge before beginning an access request. See WAITxEDGEDETECTIONSTATUS in the GPMC_IRQSTATUS register (if enabled).

One example where software must poll the WAIT pin is NAND mode where the NAND device might assert WAIT for up to 50uS which is too long for the hardware wait monitoring.
Refer to AM64x TRM sections...
12.3.3.4.11.2 NAND Device-Ready Pin
12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt

Regards,
Mark

Hi Sreenivasa, Mark,

Thank you for your response, but sorry could I confirm again your answers to the following inquiries ?

1.  If the WAIT is asserted before the AM64 issues an access request on the parallel bus, will the AM64 wait for the access request, or will it issue the request and wait for the response?

The former is correct ?  AM64 can't issue an access request until the WAIT is deasserted ?

2.  They are considering the memory connection configuration, and would like to confirm whether the parallel bus can be made into a multi-master configuration. Is it possible ?

Is multi-master configuration possible on the parallel bus ?  Is it possible to add another Master device on the bus ?

Thanks and regards,

Hideaki

Hello Hideaki

Please refer below

Hideaki Matsumoto said:

1.  If the WAIT is asserted before the AM64 issues an access request on the parallel bus, will the AM64 wait for the access request, or will it issue the request and wait for the response?

The former is correct ?  AM64 can't issue an access request until the WAIT is deasserted ?

However, before beginning an access request software can poll the WAITxSTATUS bit of the GPMC_STATUS register which indicates the WAIT status state (where x = 0 to 1).

Or software can respond to an interrupt on a WAIT pin edge before beginning an access request. See WAITxEDGEDETECTIONSTATUS in the GPMC_IRQSTATUS register (if enabled).

One example where software must poll the WAIT pin is NAND mode where the NAND device might assert WAIT for up to 50uS which is too long for the hardware wait monitoring.
Refer to AM64x TRM sections...
12.3.3.4.11.2 NAND Device-Ready Pin
12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt

Regards,

Sreenivasa

Hello Hideaki

Please refer below

2.  They are considering the memory connection configuration, and would like to confirm whether the parallel bus can be made into a multi-master configuration. Is it possible ?

Is multi-master configuration possible on the parallel bus ?  Is it possible to add another Master device on the bus ?

Below threads help in understanding the AM64X GPMC can be a master (not slave)

(+) AM2431: Slave mode on GPMC - Arm-based microcontrollers - INTERNAL forum - Arm-based microcontrollers - INTERNAL - TI E2E support forums

AM5708: GPMC - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hello Hideaki

Please refer below

2.  They are considering the memory connection configuration, and would like to confirm whether the parallel bus can be made into a multi-master configuration. Is it possible ?

Is multi-master configuration possible on the parallel bus ?  Is it possible to add another Master device on the bus ?

Below threads help in understanding the AM64X GPMC can be a master (not slave)

(+) AM2431: Slave mode on GPMC - Arm-based microcontrollers - INTERNAL forum - Arm-based microcontrollers - INTERNAL - TI E2E support forums

AM5708: GPMC - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hello Hideaki

Q2 contd..

Kallikuppa Sreenivasa said:

2.  They are considering the memory connection configuration, and would like to confirm whether the parallel bus can be made into a multi-master configuration. Is it possible ?

Is multi-master configuration possible on the parallel bus ?  Is it possible to add another Master device on the bus ?

GPMC can work as master only.

The multi-master configuration is feasible maybe with some additional software and GPIO handshaking (or maybe through WAIT monitoring and modified software).

This is not something we have validated. 

Do you have some thoughts if customer has a setup that could be used to validate the multi-master configuration.

regards,

Sreenivasa