• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 437 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RapidIO: Reduce SRIO transfer rate from 3.125 to about 2.5 - in only one direction

Eddie3909
Guru 10385 points

Hi

DSP: C6472, DIO lib 1.1.0

Because of target memory access issues, I have to reduce the tx speed of the SRIO data. We are currently configured for 3.125 which we need for writes to the DSP, but for writes from the DSP to the target, the max can only be about 2 Gbps.

Is there a way to configure SRIO to use wait states between packets to reduce the average DSP to target transfer rate?

I've read in the RapidIO Interconnect Spec Rev1.2 that there is packet pacing symbols. Can these be used somehow? Is there a way to configure SRIO to force pacing symbol insertions?

I tried NWRITEs and the NWRITE overhead does not appear to reduce the transmit rate significantly relative to SWRITEs.

We have added high speed FIFO's to the target infront of its memory but we are still filling up our SRIO tx fifo (aka getting outbound credit errors) since our transfer size is large (about 0.5 MB).

Cheers

Eddie

  • 0
    TI__Mastermind 23525 points

    Eddie,

    First, as you are probably aware, both directions of an SRIO link have to be at the same data rate between link partners.  Given that, you are looking for a way to slow down the transactions from a DSP TX point of view.  There are a limited number of  ways to do this. The SRIO peripheral hardware doesn't have any way of throttling the TX data though.  Once the statemachines apply for a outbound credit, there is not way to stop the attempts and avoid getting the outbound credit CC.  So you either need to be able to handle this situation, which the DIOLib EDMA streaming example does, or you need to artificially delay (with a software timer) the outbound transactions being written to the SRIO LSUs.  This could be done by limiting the LSU transaction size to less than the number of total buffers in the DSP TX and target RX path combined, then waiting an amount of time before reprogramming the LSU.  The time you would need to wait is the time for the buffers in the TX/RX path to empty.

    Regards,

    Travis

     

  • 0 in reply to tscheck
    Guru 10385 points

    Thanks Travis

    Update: You can use interrupt pacing to slow down SRIO streaming. See the thread

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/105729/376055.aspx