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Problems with SDRAM read and write in C6713B-200M DSP board

Jerome Lau
Prodigy 130 points

There are some strange problems with SDRAM read and write. A 1M*32bits*4banks SDRAM is used in my C6713B-200M board, that is for a 32-bit data read and write manipulation, the maximum address range is 0x400000(4M).

I have developed two same boards with C6713B-200M. SDRAM works correctly in one board but some problems in other board. I have exchanged the two SDRAM chips and am sure that both of them works correctly.

In the board that SDRAM can't work properly, some strange and interesting problems can be found when view the SDRAM memory.

When i write data to SDRAM (32-bit mode) within the address range 0x10000(64k), the data writen to and read from SDRAM is correct. But when I increase the address range, the data is not correct  and the D16 is always high. The following program and the corresponding result will explain more clear the problems are.

#define BUFFER_SIZE  0x10000

 Src_StartAdd = (Uint32 *)0x80000000; 

for(i=0;i < BUFFER_SIZE;i++)
 {
  *(Src_StartAdd++) = i;
 }

when BUFFER_SIZE  is set to 0x10000(the maximum right result range), the data is correct, that is *(0x80000000) = 0x00000000,  *(0x80000004) = 0x00000001  and so on. But when BUFFER_SIZE is greater than 0x10000, the data is all wrong and there is always one bit D16  high in all data, that is *(0x80000000) = 0x00010000,  *(0x80000004) = 0x00010001 , and so on.....

Any suggestion would be greatly appreciated...

 

  • 0
    TI__Guru* 84110 points

    Since you have confirmed that the SDRAM chips themselves are good, the most likely problem is a short or error on the wiring between the C6713B and the SDRAM. There are several tests you can try that may help you narrow down the failure.

    My guess is that there is an address line shorted to D16, and it is probably the address line associated with the 0x10000 address offset.

    The simplest memory test for this would be to walk a 1 across the data bus with the address offset = 0, then do that again for each address offset with a 1 walked across it.

    The most exhaustive test would be a true walking-ones test where you fill the memory with 0's, then write a 1 to a single bit and read/test every word in the memory. Unfortunately, for a large SDRAM this test can take a long time, like hours or days, without some serious optimization at the function and system level. At the function level, this would mean assembly-optimized testing and the use of EDMA to get the data to internal memory for comparing to 0. At the system level, this would mean reducing the range of the reads to relevant blocks or ranges.

    So we can start by hoping that the simple test works good enough to find a wiring problem.