J721S2XSOMXEVM: strange boot problems for custom board with 4G ram

// SPDX-License-Identifier: GPL-2.0
/*
 *  Reference is k3-j721s2-r5-common-proc-board.dts
 */

/dts-v1/;

#include "custom-common.dtsi"
#include "custom-2gb-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"

/ {
    chosen {
        firmware-loader = &fs_loader0;
        stdout-path = &mcu_uart0;
        tick-timer = &timer1;
    };

    aliases {
        remoteproc0 = &sysctrler;
        remoteproc1 = &a72_0;
        remoteproc2 = &main_r5fss0_core0;
        remoteproc3 = &main_r5fss0_core1;
        };

    fs_loader0: fs_loader@0 {
        compatible = "u-boot,fs-loader";
        u-boot,dm-pre-reloc;
        };

    a72_0: a72@0 {
        compatible = "ti,am654-rproc";
        reg = <0x0 0x00a90000 0x0 0x10>;
        power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
                <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
        resets = <&k3_reset 202 0>;
        clocks = <&k3_clks 61 1>;
        assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
        assigned-clock-parents = <&k3_clks 61 2>;
        assigned-clock-rates = <200000000>, <2000000000>;
        ti,sci = <&sms>;
        ti,sci-proc-id = <32>;
        ti,sci-host-id = <10>;
        u-boot,dm-spl;
    };

    clk_200mhz: dummy_clock_200mhz {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <200000000>;
        u-boot,dm-spl;
    };

    clk_19_2mhz: dummy_clock_19_2mhz {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <19200000>;
        u-boot,dm-spl;
    };
};

&cbass_mcu_wakeup {
    sa3_secproxy: secproxy@44880000 {
        u-boot,dm-spl;
        compatible = "ti,am654-secure-proxy";
        reg = <0x0 0x44880000 0x0 0x20000>,
              <0x0 0x44860000 0x0 0x20000>,
              <0x0 0x43600000 0x0 0x10000>;
        reg-names = "rt", "scfg", "target_data";
        #mbox-cells = <1>;
    };

    mcu_secproxy: secproxy@2a380000 {
        compatible = "ti,am654-secure-proxy";
        reg = <0x0 0x2a380000 0x0 0x80000>,
              <0x0 0x2a400000 0x0 0x80000>,
              <0x0 0x2a480000 0x0 0x80000>;
        reg-names = "rt", "scfg", "target_data";
        #mbox-cells = <1>;
        u-boot,dm-spl;
    };

    sysctrler: sysctrler {
        compatible = "ti,am654-system-controller";
        mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
        mbox-names = "tx", "rx", "boot_notify";
        u-boot,dm-spl;
    };

    dm_tifs: dm-tifs {
        compatible = "ti,j721e-dm-sci";
        ti,host-id = <3>;
        ti,secure-host;
        mbox-names = "rx", "tx";
        mboxes= <&mcu_secproxy 21>,
            <&mcu_secproxy 23>;
        u-boot,dm-spl;
    };
};

&main_pmx0 {
    main_uart8_pins_default: main-uart8-pins-default {
        pinctrl-single,pins = <
			J721S2_IOPAD(0x038, PIN_INPUT, 11) /* (AB28) MCASP0_ACLKX.UART8_RXD */
			J721S2_IOPAD(0x03c, PIN_INPUT, 11) /* (U27) MCASP0_AFSX.UART8_TXD */
		>;
    };
};

&wkup_pmx0 {
    mcu_uart0_pins_default: mcu-uart0-pins-default {
        u-boot,dm-spl;
        pinctrl-single,pins = <
            J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
            J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
        >;
    };

    mymcu_ospi1_pins_default: mymcu_ospi1_pins_default {
        pinctrl-single,pins = <
            J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT_PULLUP, 0) /* (D19) MCU_OSPI0_CLK */
            J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT_PULLUP, 0) /* (F15) MCU_OSPI0_CSn0 */
            J721S2_WKUP_IOPAD(0x00c, PIN_INPUT_PULLUP, 0) /* (C19) MCU_OSPI0_D0 */
            J721S2_WKUP_IOPAD(0x010, PIN_INPUT_PULLUP, 0) /* (F16) MCU_OSPI0_D1 */
            J721S2_WKUP_IOPAD(0x014, PIN_INPUT_PULLUP, 0) /* (G15) MCU_OSPI0_D2 */
            J721S2_WKUP_IOPAD(0x018, PIN_INPUT_PULLUP, 0) /* (F18) MCU_OSPI0_D3 */
            J721S2_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 0) /* (E19) MCU_OSPI0_D4 */
            J721S2_WKUP_IOPAD(0x020, PIN_INPUT_PULLUP, 0) /* (G19) MCU_OSPI0_D5 */
            J721S2_WKUP_IOPAD(0x024, PIN_INPUT_PULLUP, 0) /* (F19) MCU_OSPI0_D6 */
            J721S2_WKUP_IOPAD(0x028, PIN_INPUT_PULLUP, 0) /* (F20) MCU_OSPI0_D7 */
            J721S2_WKUP_IOPAD(0x008, PIN_INPUT_PULLDOWN, 0) /* (E18) MCU_OSPI0_DQS */
            J721S2_WKUP_IOPAD(0x004, PIN_OUTPUT_PULLUP, 0) /* (E20) MCU_OSPI0_LBCLKO */
        >;
    };
};

&sms {
    mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
    mbox-names = "tx", "rx", "notify";
    ti,host-id = <4>;
    ti,secure-host;
    u-boot,dm-spl;
};

&wkup_uart0 {
    status = "disabled";
};

&mcu_uart0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&mcu_uart0_pins_default>;
};

&main_uart8 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&main_uart8_pins_default>;
};

&main_uart8_pins_default {
	u-boot,dm-spl;
};

&main_sdhci0 {
    /delete-property/ power-domains;
    /delete-property/ assigned-clocks;
    /delete-property/ assigned-clock-parents;
    clock-names = "clk_xin";
    clocks = <&clk_200mhz>;
    ti,driver-strength-ohm = <50>;
    non-removable;
    status="okay";
};

&usbss0 {
    status = "disabled";
};

&usb0 {
    status = "disabled";
    // Add support
};

&mcu_ringacc {
    ti,sci = <&dm_tifs>;
};

&mcu_udmap {
    ti,sci = <&dm_tifs>;
};

&ospi0 {
    reg = <0x0 0x47040000 0x0 0x100>,
          <0x0 0x50000000 0x0 0x8000000>;

    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&mymcu_ospi1_pins_default>;
    flash@0{
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        spi-tx-bus-width = <8>;
        spi-rx-bus-width = <8>;
        spi-max-frequency = <25000000>;
        cdns,tshsl-ns = <60>;
        cdns,tsd2d-ns = <60>;
        cdns,tchsh-ns = <60>;
        cdns,tslch-ns = <60>;
        cdns,read-delay = <0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

#include "custom-u-boot.dtsi"

/* Lets now HACK things so that we get our config back */
/ {
    chosen {
        firmware-loader = &fs_loader0;
        stdout-path = &main_uart8;
        tick-timer = &timer1;
    };
    aliases {
        remoteproc0 = &sysctrler;
        remoteproc1 = &a72_0;
        remoteproc2 = &main_r5fss0_core0;
        remoteproc3 = &main_r5fss0_core1;
        spi0 = &ospi0;
        };

};

// Only single DDR slot used
&memorycontroller1 {
	status = "disabled";
};

// SPDX-License-Identifier: GPL-2.0
/*
 *
 */

/dts-v1/;

#include "k3-j721s2.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	memory@80000000 {
		device_type = "memory";
		/* 4 GB RAM */
		reg = <0x00 0x80000000 0x00 0x80000000>,
		      <0x08 0x80000000 0x00 0x80000000>;
	};

	/* Reserving memory regions still pending */
	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>;
			alignment = <0x1000>;
			no-map;
		};
	};
};

&main_mcan16 {
	status = "disabled";
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mymcu_ospi1_pins_default>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&mailbox0_cluster0 {
	interrupts = <436>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster1 {
	interrupts = <432>;

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster2 {
	interrupts = <428>;

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster3 {
	status = "disabled";
};

&mailbox0_cluster4 {
	interrupts = <420>;

	mbox_c71_0: mbox-c71-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c71_1: mbox-c71-1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster5 {
	status = "disabled";
};

&mailbox0_cluster6 {
	status = "disabled";
};

&mailbox0_cluster7 {
	status = "disabled";
};

&mailbox0_cluster8 {
	status = "disabled";
};

&mailbox0_cluster9 {
	status = "disabled";
};

&mailbox0_cluster10 {
	status = "disabled";
};

&mailbox0_cluster11 {
	status = "disabled";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
	status = "disabled";
};

&mcu_r5fss0_core1 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
	status = "disabled";
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
	status = "disabled";
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
	status = "disabled";
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
	status = "disabled";
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
	status = "disabled";
};

&c71_0 {
	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
	status = "disabled";
};

&c71_1 {
	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
	status = "disabled";
};

// SPDX-License-Identifier: GPL-2.0
/*
 * Reference is k3-j721s2-common-proc-board-u-boot.dtss
 */

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		tick-timer = &timer1;
	};

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart8;
		i2c0 = &wkup_i2c0;
		i2c1 = &mcu_i2c0;
		i2c2 = &mcu_i2c1;
		i2c3 = &main_i2c0;
		ethernet0 = &main_cpsw_port1;
		spi0 = &ospi0;
		mmc0 = &main_sdhci0;
	};
};

&cbass_main {
	u-boot,dm-spl;
};

&main_navss {
	u-boot,dm-spl;
};

&cbass_mcu_wakeup {
	u-boot,dm-spl;

	timer1: timer@40400000 {
		compatible = "ti,omap5430-timer";
		reg = <0x0 0x40400000 0x0 0x80>;
		ti,timer-alwon;
		clock-frequency = <25000000>;
		u-boot,dm-spl;
	};

	chipid@43000014 {
		u-boot,dm-spl;
	};
};

&mcu_navss {
	u-boot,dm-spl;
};

&mcu_ringacc {
	reg =   <0x0 0x2b800000 0x0 0x400000>,
		<0x0 0x2b000000 0x0 0x400000>,
		<0x0 0x28590000 0x0 0x100>,
		<0x0 0x2a500000 0x0 0x40000>,
		<0x0 0x28440000 0x0 0x40000>;
	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
	u-boot,dm-spl;
};

&mcu_udmap {
	reg =   <0x0 0x285c0000 0x0 0x100>,
		<0x0 0x284c0000 0x0 0x4000>,
		<0x0 0x2a800000 0x0 0x40000>,
		<0x0 0x284a0000 0x0 0x4000>,
		<0x0 0x2aa00000 0x0 0x40000>,
		<0x0 0x28400000 0x0 0x2000>;
	reg-names = "gcfg", "rchan", "rchanrt", "tchan",
		    "tchanrt", "rflow";
	u-boot,dm-spl;
};

&secure_proxy_main {
	u-boot,dm-spl;
};

&sms {
	u-boot,dm-spl;
	k3_sysreset: sysreset-controller {
		compatible = "ti,sci-sysreset";
		u-boot,dm-spl;
	};
};

&main_pmx0 {
	u-boot,dm-spl;
};

// &main_mmc0_pins_default {
// 	u-boot,dm-spl;
// };

// &main_usbss0_pins_default {
// 	u-boot,dm-spl;
// };

&main_uart8 {
	u-boot,dm-spl;
};

&wkup_pmx0 {
	u-boot,dm-spl;
};

&k3_pds {
	u-boot,dm-spl;
};

&k3_clks {
	u-boot,dm-spl;
};

&k3_reset {
	u-boot,dm-spl;
};


&mcu_uart0 {
	u-boot,dm-spl;
};

&wkup_uart0 {
	u-boot,dm-spl;
};

&fss {
	u-boot,dm-spl;
};

&mcu_cpsw {
	reg = <0x0 0x46000000 0x0 0x200000>,
	      <0x0 0x40f00200 0x0 0x8>;
	reg-names = "cpsw_nuss", "mac_efuse";
	/delete-property/ ranges;

	cpsw-phy-sel@40f04040 {
        	compatible = "ti,am654-cpsw-phy-sel";
		reg= <0x0 0x40f04040 0x0 0x4>;
		reg-names = "gmii-sel";
        };
};

&main_cpsw {
	/delete-property/ ranges;

	cpsw-phy-sel@104034 {
        	compatible = "ti,am654-cpsw-phy-sel";
		reg= <0x0 0x104034 0x0 0x4>;
		reg-names = "gmii-sel";
        };
};

&mymcu_ospi1_pins_default {
	u-boot,dm-spl;
};

&main_r5fss0 {
	ti,cluster-mode = <0>;
};

&main_r5fss1 {
	ti,cluster-mode = <0>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>, <&wiz0_pll0_refclk>;
	assigned-clock-parents = <&k3_clks 365 40>, <&k3_clks 365 75>;
};

&serdes_ln_ctrl {
	u-boot,mux-autoprobe;
};

&usb_serdes_mux {
	u-boot,mux-autoprobe;
};

&ospi0 {
	u-boot,dm-spl;

	flash@0 {
		cdns,phy-mode;
		u-boot,dm-spl;

		partition@3fc0000 {
			label = "ospi.phypattern";
			reg = <0x3fc0000 0x40000>;
			u-boot,dm-spl;
		};
	};
};

&main_sdhci0 {
	u-boot,dm-spl;
};

// SPDX-License-Identifier: GPL-2.0
/*
 * Reference is k3-j721s2-common-proc-board.dts
 */

/dts-v1/;

#include "custom-common.dtsi"
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
    compatible = "ti,j721s2-evm", "ti,j721s2";
    model = "custom";

    aliases {
        serial0 = &wkup_uart0;
        serial1 = &mcu_uart0;
        serial2 = &main_uart8;
        serial3 = &main_uart1;
        serial4 = &main_uart2;
        serial5 = &main_uart3;
        serial6 = &main_uart4;
        serial7 = &main_uart5;
        serial8 = &main_uart6;
        serial9 = &main_uart7;
        serial10 = &main_uart8;
        serial11 = &main_uart9;
        mmc0 = &main_sdhci0;
        spi0 = &ospi0;
        ethernet0 = &main_cpsw_port1;
	};

    chosen {
        stdout-path = "serial10:115200n8";
        bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000";
    };
};

&main_pmx0 {
    main_uart8_pins_default: main-uart8-pins-default {
       pinctrl-single,pins = <
			J721S2_IOPAD(0x038, PIN_INPUT, 11) /* (AB28) MCASP0_ACLKX.UART8_RXD */
			J721S2_IOPAD(0x03c, PIN_INPUT, 11) /* (U27) MCASP0_AFSX.UART8_TXD */
		>;
    };

	main_spi0_pins_default: main_spi0_pins_default {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AH27) SPI0_CLK */
			J721S2_IOPAD(0x0cc, PIN_OUTPUT_PULLUP, 0) /* (AE27) SPI0_CS0 */
            /*J721S2_IOPAD(0x0d8, PIN_INPUT, 0)*/ /* (AG26) SPI0_D0 */ 
			/*J721S2_IOPAD(0x0dc, PIN_OUTPUT, 0)*/ /* (AH26) SPI0_D1 */
            /* SPI PIN管脚修改*/
             J721S2_IOPAD(0x0d8, PIN_OUTPUT, 0)  /* (AG26) SPI0_D0 */
             J721S2_IOPAD(0x0dc, PIN_INPUT, 0)  /* (AH26) SPI0_D1 */
		>;
	};

	main_gpio0_pins_default: main_gpio0_pins_default {
		pinctrl-single,pins = <
            J721S2_IOPAD(0x07c, PIN_OUTPUT, 7) /* (T27) MCASP0_AXR3.GPIO0_31 GPIO_拉高 */
			J721S2_IOPAD(0x0c8, PIN_OUTPUT_PULLDOWN, 7) /* (AD28) RESET_N_PPP2ETHSW */
			J721S2_IOPAD(0x0c4, PIN_OUTPUT_PULLDOWN, 7) /* (AB26) RESET_N_PPP2ETHPHY234 */
		>;
	};

	main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
			J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
		>;
	};

	rgmii1_pins_default: rgmii1_pins_default {
		pinctrl-single,pins = <
			J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
			J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
			J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
			J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
			J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
			J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
			J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
			J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
			J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
			J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
			J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
			J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
		>;
	};
};

&wkup_pmx0 {
    mymcu_ospi1_pins_default: mymcu_ospi1_pins_default {
        pinctrl-single,pins = <
            J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT_PULLUP, 0) /* (D19) MCU_OSPI0_CLK */
            J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT_PULLUP, 0) /* (F15) MCU_OSPI0_CSn0 */
            J721S2_WKUP_IOPAD(0x00c, PIN_INPUT_PULLUP, 0) /* (C19) MCU_OSPI0_D0 */
            J721S2_WKUP_IOPAD(0x010, PIN_INPUT_PULLUP, 0) /* (F16) MCU_OSPI0_D1 */
            J721S2_WKUP_IOPAD(0x014, PIN_INPUT_PULLUP, 0) /* (G15) MCU_OSPI0_D2 */
            J721S2_WKUP_IOPAD(0x018, PIN_INPUT_PULLUP, 0) /* (F18) MCU_OSPI0_D3 */
            J721S2_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 0) /* (E19) MCU_OSPI0_D4 */
            J721S2_WKUP_IOPAD(0x020, PIN_INPUT_PULLUP, 0) /* (G19) MCU_OSPI0_D5 */
            J721S2_WKUP_IOPAD(0x024, PIN_INPUT_PULLUP, 0) /* (F19) MCU_OSPI0_D6 */
            J721S2_WKUP_IOPAD(0x028, PIN_INPUT_PULLUP, 0) /* (F20) MCU_OSPI0_D7 */
            J721S2_WKUP_IOPAD(0x008, PIN_INPUT_PULLDOWN, 0) /* (E18) MCU_OSPI0_DQS */
            J721S2_WKUP_IOPAD(0x004, PIN_OUTPUT_PULLUP, 0) /* (E20) MCU_OSPI0_LBCLKO */
        >;
    };

    // Taken over by IU core
    // mymcu_cpsw2g1_pins_default: mymcu_cpsw2g1_pins_default {
    //     pinctrl-single,pins = <
    //         J721S2_WKUP_IOPAD(0x08c, PIN_INPUT_PULLDOWN, 0) /* (C22) MCU_RGMII1_RD2 */
    //         J721S2_WKUP_IOPAD(0x088, PIN_INPUT_PULLDOWN, 0) /* (D23) MCU_RGMII1_RD3 */
    //         J721S2_WKUP_IOPAD(0x084, PIN_INPUT_PULLDOWN, 0) /* (D22) MCU_RGMII1_RXC */
    //         J721S2_WKUP_IOPAD(0x094, PIN_INPUT_PULLDOWN, 0) /* (B22) MCU_RGMII1_RD0.MCU_RMII1_RXD0 */
    //         J721S2_WKUP_IOPAD(0x090, PIN_INPUT_PULLDOWN, 0) /* (B21) MCU_RGMII1_RD1.MCU_RMII1_RXD1 */
    //         J721S2_WKUP_IOPAD(0x06c, PIN_INPUT_PULLDOWN, 0) /* (E23) MCU_RGMII1_RX_CTL */
    //         J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
    //         J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
    //         J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
    //         J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
    //         J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
    //         J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
    //     >;
    // };

    // mcu_mdio_pins_default: mcu-mdio-pins-default {
    //     pinctrl-single,pins = <
    //         J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
    //         J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
    //     >;
    // };

    mywkup_gpio0_pins_default: mywkup_gpio0_pins_default {
		pinctrl-single,pins = <
			J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT_PULLDOWN, 7) /* (C23) WKUP_GPIO0_4 */
			J721S2_WKUP_IOPAD(0x0d4, PIN_OUTPUT_PULLDOWN, 7) /* (F26) WKUP_GPIO0_5 */
			J721S2_WKUP_IOPAD(0x0d8, PIN_OUTPUT_PULLDOWN, 7) /* (E25) WKUP_GPIO0_6 */
			J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT_PULLUP, 7) /* (F28) WKUP_GPIO0_7 */
			J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT_PULLUP, 7) /* (F27) WKUP_GPIO0_10 */
			J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT_PULLDOWN, 7) /* (F25) WKUP_GPIO0_11 */
			J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT_PULLDOWN, 7) /* (A19) MCU_OSPI1_CLK.WKUP_GPIO0_31 */
			J721S2_WKUP_IOPAD(0x044, PIN_OUTPUT_PULLDOWN, 7) /* (B20) MCU_OSPI1_LBCLKO.WKUP_GPIO0_32 */
			J721S2_WKUP_IOPAD(0x048, PIN_OUTPUT_PULLDOWN, 7) /* (B19) MCU_OSPI1_DQS.WKUP_GPIO0_33 */
			J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT_PULLDOWN, 7) /* (D21) MCU_OSPI1_D0.WKUP_GPIO0_34 */
			J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT_PULLDOWN, 7) /* (G20) MCU_OSPI1_D1.WKUP_GPIO0_35 */
			J721S2_WKUP_IOPAD(0x054, PIN_OUTPUT_PULLDOWN, 7) /* (C20) MCU_OSPI1_D2.WKUP_GPIO0_36 */
			J721S2_WKUP_IOPAD(0x058, PIN_OUTPUT_PULLDOWN, 7) /* (A20) MCU_OSPI1_D3.WKUP_GPIO0_37 */
			J721S2_WKUP_IOPAD(0x05c, PIN_INPUT_PULLUP, 7) /* (D20) MCU_OSPI1_CSn0.WKUP_GPIO0_38 */
			J721S2_WKUP_IOPAD(0x060, PIN_INPUT_PULLUP, 7) /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
			J721S2_WKUP_IOPAD(0x17c, PIN_OUTPUT_PULLDOWN, 7) /* (J26) WKUP_GPIO0_57 */
			J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 7) /* (D28) WKUP_UART0_RXD.WKUP_GPIO0_58 */
			J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT_PULLDOWN, 7) /* (D27) WKUP_UART0_TXD.WKUP_GPIO0_59 */
			J721S2_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
			J721S2_WKUP_IOPAD(0x184, PIN_OUTPUT_PULLDOWN, 7) /* (J27) WKUP_GPIO0_67 */
			J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 7) /* (L25) MCU_ADC0_AIN0.WKUP_GPIO0_71 */
			J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 7) /* (K25) MCU_ADC0_AIN1.WKUP_GPIO0_72 */
			J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 7) /* (M24) MCU_ADC0_AIN2.WKUP_GPIO0_73 */
			J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 7) /* (L24) MCU_ADC0_AIN3.WKUP_GPIO0_74 */
			J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 7) /* (L27) MCU_ADC0_AIN4.WKUP_GPIO0_75 */
			J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 7) /* (K24) MCU_ADC0_AIN5.WKUP_GPIO0_76 */
			J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 7) /* (M26) MCU_ADC0_AIN7.WKUP_GPIO0_78 */
			J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 7) /* (P25) MCU_ADC1_AIN0.WKUP_GPIO0_79 */
			J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 7) /* (R25) MCU_ADC1_AIN1.WKUP_GPIO0_80 */
			J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 7) /* (P27) MCU_ADC1_AIN3.WKUP_GPIO0_82 */
			J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 7) /* (N25) MCU_ADC1_AIN4.WKUP_GPIO0_83 */
        J721S2_WKUP_IOPAD(0x120, PIN_OUTPUT_PULLDOWN, 7) 
		>;
	};
};

&wkup_gpio0 {
     status = "okay";
     pinctrl-names = "default";
     pinctrl-0 = <&mywkup_gpio0_pins_default>;
     eth_phy1_wakeup {
         gpio-hog;
         gpios = <56 GPIO_ACTIVE_HIGH>; // G27
         output-high;
         line-name = "RESET_N_PPP2ETHSW";
     };
};


// &wkup_gpio0 {
//     status = "okay";
//     pinctrl-names = "default";
//     pinctrl-0 = <&mywkup_gpio0_pins_default>;
//     eth_phy1_wakeup {
//         gpio-hog;
//         gpios = <32 GPIO_ACTIVE_HIGH>; // B20
//         output-high;
//         line-name = "eth_phy1_wakeup";
//     };
// };

// &mcu_cpsw {
//     status = "okay";
//     pinctrl-names = "default";
//     pinctrl-0 = <&mymcu_cpsw2g1_pins_default &mcu_mdio_pins_default>;
//     mac-address = [ 02 ad c5 10 b0 00 ];


// };

// &davinci_mdio {
//     status = "okay";
//     bus_freq = <20000>;
//     phy0: ethernet-phy@0 {
//         reg = <0>;
//     };
// };

// &cpsw_port1 {
//     phy-mode = "rgmii-rxid";
//     phy-handle = <&phy0>;
// };

&davinci_mdio {
  status = "disabled";  
};

&mcu_cpsw {
  status = "disabled";  
};

&main_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_gpio0_pins_default>;

    /*+ +*/
    p31 {
		gpio-hog;
		gpios = <31 0>;
		output-high;
		line-name = "RESET_N_PPP2ETHPHY234";
	};
    /*+ +*/
    
	p49 {
		gpio-hog;
		gpios = <49 0>;
		output-high;
		line-name = "RESET_N_PPP2ETHPHY234";
	};

	p50 {
		gpio-hog;
		gpios = <50 0>;
		output-high;
		line-name = "RESET_N_PPP2ETHSW";
	};

};

&main_gpio2 {
    status = "disabled";
};

&main_gpio4 {
    status = "disabled";
};

&main_gpio6 {
    status = "disabled";
};

&wkup_gpio1 {
    status = "disabled";
};

&wkup_uart0 {
    status = "reserved";
};

&main_uart0 {
    status = "disabled";
};

&main_uart1 {
    status = "disabled";
};

&main_uart2 {
    status = "disabled";
};

&main_uart3 {
    status = "disabled";
};

&main_uart4 {
    status = "disabled";
};

&main_uart5 {
    status = "disabled";
};

&main_uart6 {
    status = "disabled";
};

&main_uart7 {
    status = "disabled";
};

&main_uart8 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&main_uart8_pins_default>;
    /* Shared with ATF on this platform */
    power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};

&main_uart9 {
    status = "disabled";
};

&main_i2c0 {
    status = "disabled";
};

&main_i2c1 {
    status = "disabled";
};

&main_i2c2 {
    status = "disabled";
};

&main_i2c3 {
    status = "disabled";
};

&main_i2c4 {
    status = "disabled";
};

&main_i2c5 {
    status = "disabled";
};

&main_i2c6 {
    status = "disabled";
};

&usbss0 {
    status = "disabled";
};

&usb0 {
    status = "disabled";
    dr_mode = "otg";
    maximum-speed = "high-speed";
};

&main_sdhci0 {
    /* eMMC */
    non-removable;
    ti,driver-strength-ohm = <50>;
    disable-wp;
    status = "okay";
};

&main_sdhci1 {
    /* SD card do not exists*/
    status = "disabled";
};

&serdes_ln_ctrl {
    status = "disabled";
    idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
              <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
};

&usb_serdes_mux {
    status = "disabled";
    idle-states = <1>; /* USB0 to SERDES lane 1 */
};

&serdes_refclk {
    clock-frequency = <100000000>;
};

&serdes0 {
    status = "disabled";
};

&pcie1_rc {
    status = "disabled";
};

&pcie1_ep {
    status = "disabled";
};

&mcu_mcan0 {
    status = "disabled";
};

&mcu_mcan1 {
    status = "disabled";
};

&main_mcan0 {
    status = "disabled";
};

&main_mcan1 {
    status = "disabled";
};

&main_mcan2 {
    status = "disabled";
};

&main_mcan3 {
    status = "disabled";
};

&main_mcan4 {
    status = "disabled";
};

&main_mcan6 {
    status = "disabled";
};

&main_mcan7 {
    status = "disabled";
};

&main_mcan8 {
    status = "disabled";
};

&main_mcan9 {
    status = "disabled";
};

&main_mcan10 {
    status = "disabled";
};

&main_mcan11 {
    status = "disabled";
};

&main_mcan12 {
    status = "disabled";
};

&main_mcan13 {
    status = "disabled";
};

&main_mcan14 {
    status = "disabled";
};

&main_mcan15 {
    status = "disabled";
};

&main_mcan17 {
    status = "disabled";
};

&ospi1 {
    /* Do not exists */
    status = "disabled";
};

&main_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&main_cpsw_mdio_pins_default
		     &rgmii1_pins_default>;
	
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&main_cpsw_port1 {
	phy-mode = "rgmii-rxid";
    mac-address = [ 02 ad c5 10 b0 01 ];
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&main_davinci_mdio {
};

&main_spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi0_pins_default>;
};

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721S2 SoC Family
 *
 * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
 *
 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

/ {

	model = "Texas Instruments K3 J721S2 SoC";
	compatible = "ti,j721s2";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		next-level-cache = <&msmc_l3>;
	};

	msmc_l3: l3-cache0 {
		compatible = "cache";
		cache-level = <3>;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	a72_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */

	};

	pmu: pmu {
		compatible = "arm,cortex-a72-pmu";
		/* Recommendation from GIC500 TRM Table A.3 */
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: bus@100000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
			 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
			 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
			 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
			 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */

			 /* MCUSS_WKUP Range */
			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
			 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;

		cbass_mcu_wakeup: bus@28380000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
				 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
				 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/

		};

	};
};

/* Now include peripherals from each bus segment */
#include "k3-j721s2-main.dtsi"
#include "k3-j721s2-mcu-wakeup.dtsi"

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
 *
 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu_wakeup {
	sms: system-controller@44083000 {
		compatible = "ti,k2g-sci";
		ti,host-id = <12>;

		mbox-names = "rx", "tx";

		mboxes= <&secure_proxy_main 11>,
			<&secure_proxy_main 13>;

		reg-names = "debug_messages";
		reg = <0x00 0x44083000 0x00 0x1000>;

		k3_pds: power-controller {
			compatible = "ti,sci-pm-domain";
			#power-domain-cells = <2>;
		};

		k3_clks: clock-controller {
			compatible = "ti,k2g-sci-clk";
			#clock-cells = <2>;
		};

		k3_reset: reset-controller {
			compatible = "ti,sci-reset";
			#reset-cells = <2>;
		};
	};

	chipid@43000014 {
		compatible = "ti,am654-chipid";
		reg = <0x00 0x43000014 0x00 0x4>;
	};

	mcu_ram: sram@41c00000 {
		compatible = "mmio-sram";
		reg = <0x00 0x41c00000 0x00 0x100000>;
		ranges = <0x00 0x00 0x41c00000 0x100000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	wkup_pmx0: pinctrl@4301c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x00 0x4301c000 0x00 0x178>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	wkup_gpio_intr: interrupt-controller@42200000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x42200000 0x00 0x400>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&sms>;
		ti,sci-dev-id = <125>;
		ti,interrupt-ranges = <16 928 16>;
	};

	mcu_conf: syscon@40f00000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x40f00000 0x0 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x40f00000 0x20000>;

		phy_gmii_sel: phy@4040 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x4040 0x4>;
			#phy-cells = <1>;
		};

	};

	wkup_uart0: serial@42300000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x42300000 0x00 0x200>;
		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 359 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_uart0: serial@40a00000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x40a00000 0x00 0x200>;
		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 149 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
	};

	wkup_gpio0: gpio@42110000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x42110000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <89>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 115 0>;
		clock-names = "gpio";
	};

	wkup_gpio1: gpio@42100000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x42100000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <89>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 116 0>;
		clock-names = "gpio";
	};

	wkup_i2c0: i2c@42120000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x42120000 0x00 0x100>;
		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 223 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_i2c0: i2c@40b00000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x40b00000 0x00 0x100>;
		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 221 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_i2c1: i2c@40b10000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x40b10000 0x00 0x100>;
		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 222 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_mcan0: can@40528000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x40528000 0x00 0x200>,
		      <0x00 0x40500000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	mcu_mcan1: can@40568000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x40568000 0x00 0x200>,
		      <0x00 0x40540000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	mcu_navss: bus@28380000{
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <267>;

		mcu_ringacc: ringacc@2b800000 {
			compatible = "ti,am654-navss-ringacc";
			reg = <0x0 0x2b800000 0x0 0x400000>,
			      <0x0 0x2b000000 0x0 0x400000>,
			      <0x0 0x28590000 0x0 0x100>,
			      <0x0 0x2a500000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <286>;
			ti,sci-rm-range-gp-rings = <0x1>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <272>;
			msi-parent = <&main_udmass_inta>;
		};

		mcu_udmap: dma-controller@285c0000 {
			compatible = "ti,j721e-navss-mcu-udmap";
			reg = <0x0 0x285c0000 0x0 0x100>,
			      <0x0 0x2a800000 0x0 0x40000>,
			      <0x0 0x2aa00000 0x0 0x40000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&sms>;
			ti,sci-dev-id = <273>;
			ti,ringacc = <&mcu_ringacc>;
			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>; /* TX_HCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>; /* RX_HCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};
	};

	mcu_cpsw: ethernet@46000000 {
		compatible = "ti,j721e-cpsw-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0x46000000 0x0 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
		dma-coherent;
		clocks = <&k3_clks 29 28>;
		clock-names = "fck";
		power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&mcu_udmap 0xf000>,
		       <&mcu_udmap 0xf001>,
		       <&mcu_udmap 0xf002>,
		       <&mcu_udmap 0xf003>,
		       <&mcu_udmap 0xf004>,
		       <&mcu_udmap 0xf005>,
		       <&mcu_udmap 0xf006>,
		       <&mcu_udmap 0xf007>,
		       <&mcu_udmap 0x7000>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			cpsw_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				ti,syscon-efuse = <&mcu_conf 0x200>;
				phys = <&phy_gmii_sel 1>;
			};
		};

		davinci_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x0 0xf00 0x0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 29 28>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,am65-cpts";
			reg = <0x0 0x3d000 0x0 0x400>;
			clocks = <&k3_clks 29 3>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	fss: syscon@47000000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x47000000 0x0 0x100>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ospi0: spi@47040000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x00 0x47040000 0x00 0x100>,
			      <0x5 0x0000000 0x1 0x0000000>;
			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			clocks = <&k3_clks 109 5>;
			assigned-clocks = <&k3_clks 109 5>;
			assigned-clock-parents = <&k3_clks 109 7>;
			assigned-clock-rates = <166666666>;
			power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ospi1: spi@47050000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x00 0x47050000 0x00 0x100>,
			      <0x7 0x0000000 0x1 0x0000000>;
			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			clocks = <&k3_clks 110 5>;
			power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

	};

	mcu_r5fss0: r5fss@41000000 {
		compatible = "ti,j721s2-r5fss";
		ti,cluster-mode = <1>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x41000000 0x00 0x41000000 0x20000>,
			 <0x41400000 0x00 0x41400000 0x20000>;
		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;

		mcu_r5fss0_core0: r5f@41000000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x41000000 0x00010000>,
			      <0x41010000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <284>;
			ti,sci-proc-ids = <0x01 0xff>;
			resets = <&k3_reset 284 1>;
			firmware-name = "j7-mcu-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		mcu_r5fss0_core1: r5f@41400000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x41400000 0x00010000>,
			      <0x41410000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <285>;
			ti,sci-proc-ids = <0x02 0xff>;
			resets = <&k3_reset 285 1>;
			firmware-name = "j7-mcu-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};
};

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/mux/mux.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>

/ {
	serdes_refclk: serdes-refclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x400000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x400000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};

		tifs-sram@1f0000 {
			reg = <0x1f0000 0x10000>;
		};

		l3cache-sram@200000 {
			reg = <0x200000 0x200000>;
		};
	};

	scm_conf: scm-conf@104000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0x00 0x00104000 0x00 0x18000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x00104000 0x18000>;

		serdes_ln_ctrl: mux-controller0 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
					<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
		};

		usb_serdes_mux: mux-controller1 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
		};
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
		      <0x00 0x01900000 0x00 0x100000>; /* GICR */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_cpsw: ethernet@c200000 {
		compatible = "ti,j721e-cpsw-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0xc200000 0x0 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
		dma-coherent;
		clocks = <&k3_clks 28 28>;
		clock-names = "fck";
		power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&main_udmap 0xc640>,
		       <&main_udmap 0xc641>,
		       <&main_udmap 0xc642>,
		       <&main_udmap 0xc643>,
		       <&main_udmap 0xc644>,
		       <&main_udmap 0xc645>,
		       <&main_udmap 0xc646>,
		       <&main_udmap 0xc647>,
		       <&main_udmap 0x4640>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			main_cpsw_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				phys = <&phy_gmii_sel 1>;
			};
		};

		main_davinci_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x0 0xf00 0x0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 28 28>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,am65-cpts";
			reg = <0x0 0x3d000 0x0 0x400>;
			clocks = <&k3_clks 28 3>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	main_gpio_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&sms>;
		ti,sci-dev-id = <148>;
		ti,interrupt-ranges = <8 360 56>;
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x120>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x200>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 146 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x200>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 350 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x200>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 351 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x200>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 352 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x200>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 353 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x200>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 354 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x200>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 355 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x200>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 356 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x200>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 357 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x200>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 358 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00600000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <145>, <146>, <147>, <148>, <149>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00610000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <154>, <155>, <156>, <157>, <158>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00620000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <163>, <164>, <165>, <166>, <167>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 113 0>;
		clock-names = "gpio";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00630000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <172>, <173>, <174>, <175>, <176>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 114 0>;
		clock-names = "gpio";
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02000000 0x00 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 214 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02010000 0x00 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 215 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02020000 0x00 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 216 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02030000 0x00 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 217 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02040000 0x00 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 218 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02050000 0x00 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 219 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02060000 0x00 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 220 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
		reg = <0x00 0x2100000 0x00 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 339 0>;
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x00 0x04f80000 0x00 0x1000>,
		      <0x00 0x04f88000 0x00 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
		clock-names =  "clk_ahb", "clk_xin";
		assigned-clocks = <&k3_clks 98 1>;
		assigned-clock-parents = <&k3_clks 98 2>;
		bus-width = <8>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
	//	ti,otap-del-sel-ddr52 = <0x6>;
	//	ti,otap-del-sel-hs200 = <0x8>;
	//	ti,otap-del-sel-hs400 = <0x5>;
		ti,itap-del-sel-legacy = <0x10>;
		ti,itap-del-sel-mmc-hs = <0xa>;
		ti,strobe-sel = <0x77>;
		ti,clkbuf-sel = <0x7>;
		ti,trm-icp = <0x8>;
	//	mmc-ddr-1_8v;
	//	mmc-hs200-1_8v;
	//	mmc-hs400-1_8v;
		dma-coherent;
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x00 0x04fb0000 0x00 0x1000>,
		      <0x00 0x04fb8000 0x00 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
		clock-names =  "clk_ahb", "clk_xin";
		assigned-clocks = <&k3_clks 99 1>;
		assigned-clock-parents = <&k3_clks 99 2>;
		bus-width = <4>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-sdr104 = <0x5>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,clkbuf-sel = <0x7>;
		ti,trm-icp = <0x8>;
		dma-coherent;
		/* Masking support for SDR104 capability */
		sdhci-caps-mask = <0x00000003 0x00000000>;
	};

	main_navss: bus@30000000 {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
		ti,sci-dev-id = <224>;
		dma-coherent;
		dma-ranges;

		main_navss_intr: interrupt-controller@310e0000 {
			compatible = "ti,sci-intr";
			reg = <0x00 0x310e0000 0x00 0x4000>;
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <227>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: msi-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x00 0x33d00000 0x00 0x100000>;
			interrupt-controller;
			#interrupt-cells = <0>;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			ti,sci = <&sms>;
			ti,sci-dev-id = <265>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster0: mailbox@31f90000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f90000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster1: mailbox@31f91000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f91000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster2: mailbox@31f92000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f92000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster3: mailbox@31f93000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f93000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster4: mailbox@31f94000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f94000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster5: mailbox@31f95000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f95000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster6: mailbox@31f96000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f96000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster7: mailbox@31f97000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f97000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster8: mailbox@31f98000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f98000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster9: mailbox@31f99000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f99000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster10: mailbox@31f9a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f9a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster11: mailbox@31f9b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f9b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg = <0x0 0x3c000000 0x0 0x400000>,
			      <0x0 0x38000000 0x0 0x400000>,
			      <0x0 0x31120000 0x0 0x100>,
			      <0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <259>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg = <0x0 0x31150000 0x0 0x100>,
			      <0x0 0x34000000 0x0 0x80000>,
			      <0x0 0x35000000 0x0 0x200000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&sms>;
			ti,sci-dev-id = <263>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 226 5>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x04104000 0x00 0x100>;
		clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 360 17>;
		power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x06000000 0x00 0x10000>,
			      <0x00 0x06010000 0x00 0x10000>,
			      <0x00 0x06020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			 interrupt-names = "host", "peripheral", "otg";
			 maximum-speed = "super-speed";
			 dr_mode = "otg";
		};
	};

	serdes_wiz0: wiz@5060000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5060000 0x0 0x5060000 0x10000>;

		assigned-clocks = <&k3_clks 365 3>;
		assigned-clock-parents = <&k3_clks 365 7>;

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 365 3>, <&serdes_refclk>;
			clock-output-names = "wiz0_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 365 3>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 365 3>, <&serdes_refclk>;
			clock-output-names = "wiz0_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 365 3>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 365 3>, <&serdes_refclk>;
			clock-output-names = "wiz0_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 365 3>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5060000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x05060000 0x00010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz0 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz0_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
		max-link-speed = <3>;
		num-lanes = <4>;
		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 276 41>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb013>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
				<0 0 0 2 &pcie1_intc 0>, /* INT B */
				<0 0 0 3 &pcie1_intc 0>, /* INT C */
				<0 0 0 4 &pcie1_intc 0>; /* INT D */

		pcie1_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie1_ep: pcie-ep@2910000 {
		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
		max-link-speed = <3>;
		num-lanes = <4>;
		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 276 41>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan14: can@2681000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02681000 0x00 0x200>,
		      <0x00 0x02688000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan15: can@2691000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02691000 0x00 0x200>,
		      <0x00 0x02698000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan16: can@26a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x026a1000 0x00 0x200>,
		      <0x00 0x026a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan17: can@26b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x026b1000 0x00 0x200>,
		      <0x00 0x026b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721s2-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5c00000 0x00010000>,
			      <0x5c10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <279>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 279 1>;
			firmware-name = "j721s2-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5d00000 0x00010000>,
			      <0x5d10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <280>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 280 1>;
			firmware-name = "j721s2-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721s2-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5e00000 0x00010000>,
			      <0x5e10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <281>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 281 1>;
			firmware-name = "j721s2-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5f00000 0x00010000>,
			      <0x5f10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <282>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 282 1>;
			firmware-name = "j721s2-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721s2-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&sms>;
		ti,sci-dev-id = <8>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 8 1>;
		firmware-name = "j721s2-c71_0-fw";
	};

	c71_1: dsp@65800000 {
		compatible = "ti,j721s2-c71-dsp";
		reg = <0x00 0x65800000 0x00 0x00080000>,
		      <0x00 0x65e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&sms>;
		ti,sci-dev-id = <11>;
		ti,sci-proc-ids = <0x31 0xff>;
		resets = <&k3_reset 11 1>;
		firmware-name = "j721s2-c71_1-fw";
	};
};

// SPDX-License-Identifier: GPL-2.0+
/*
 * Board specific initialization for J721S2 custom
 *
 * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
 *	David Huang <d-huang@ti.com>
 *
 */

#include <stdbool.h>
#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <generic-phy.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <linux/delay.h>

#include "sja1105.h"

DECLARE_GLOBAL_DATA_PTR;

int board_init(void)
{
	return 0;
}

int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
	/* 2GB */
	gd->ram_size = 0x100000000;
#else
	gd->ram_size = 0x80000000;
#endif

	return 0;
}

ulong board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_PHYS_64BIT
	/* Limit RAM used by U-Boot to the DDR low region */
	if (gd->ram_top > 0x100000000)
		return 0x100000000;
#endif

	return gd->ram_top;
}

int dram_init_banksize(void)
{
	/* Bank 0 declares the memory available in the DDR low region (2GB) */
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = 0x80000000;
	gd->ram_size = 0x80000000;

#ifdef CONFIG_PHYS_64BIT
	/* Bank 1 declares the memory available in the DDR high region (0GB) */
	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
	gd->bd->bi_dram[1].size = 0x80000000;
	gd->ram_size = 0x100000000;
#endif

	return 0;
}

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	if (!strcmp(name, "custom"))
		return 0;
	/* legacy */
	if (!strcmp(name, "k3-j721s2-common-proc-board"))
		return 0;

	return -1;
}
#endif

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
	int ret;

	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
	if (ret < 0)
		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
					 "sram@70000000");
	if (ret)
		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);

	return ret;
}
#endif

int do_board_detect(void)
{
	int ret = 0;
	return ret;
}

int checkboard(void)
{
	/* Add detection once there is a B1 */
	printf("Board: custom rev %s\n", "0");

	return 0;
}

static void setup_board_info(void)
{
	env_set("board_name", "custom");
	env_set("board_rev", "0");
	env_set("board_software_revision", "0");
	env_set("board_serial", "0");
}

int board_late_init(void)
{
	setup_board_info();

#ifdef CONFIG_TARGET_J721S2_custom
	udelay(500);
	init_sja1105();
#endif

	return 0;
}

void spl_board_init(void)
{
}

▒
U-Boot SPL 2021.01-g7a30174351 (May 04 2023 - 12:07:24 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
SPL initial stack usage: 13472 bytes
Trying to boot from SPI
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.6(release):v2.7-rc0-dirty
NOTICE:  BL31: Built : 07:18:51, Mar  9 2023
I/TC:
I/TC: OP-TEE version: 3.17.0-125-g15a746d28 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Thu 09 Mar 2023 07:45:38 AM UTC aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2021.01-g7a30174351 (May 03 2023 - 12:26:45 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
Trying to boot from SPI
cadence_spi spi@47040000: Can't get reset: -2
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled


U-Boot 2021.01-g7a30174351 (May 03 2023 - 12:26:45 +0000)

SoC:   J721S2 SR1.0 GP
Model: CUSTOM
Board: CUSTOM
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   mmc@4f80000: 0
Loading Environment from FAT... OK
In:    serial@2880000
Out:   serial@2880000
Err:   serial@2880000
am65_cpsw_nuss ethernet@c200000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
cadence_spi spi@47040000: Can't get reset: -2
Initializing SJA1105... done
Net:   eth0: ethernet@c200000port@1
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0(part 0) is current device
SD/MMC found on device 0
Failed to load 'boot.scr'
1011 bytes read in 0 ms
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
## Error: "main_cpsw0_qsgmii_phyinit" not defined
31586816 bytes read in 1354 ms (22.2 MiB/s)
59194 bytes read in 4 ms (14.1 MiB/s)
224 bytes read in 1 ms (218.8 KiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008feee000, end 000000008fffffff ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 5.10.120-g889d3a89cbe8-dirty (uif56050@jdd1062u) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Fri May 5 22:07:54 CST 2023
[    0.000000] Machine model: CUSTOM 4G
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002880000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node ippu-r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node ippu-r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node spu-r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node spu-r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 58 MiB
[    0.000000] OF: reserved mem: initialized node ippu-r5f-memory-hwa@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node cvu-c7-dma-memory@aa000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa100000, size 79 MiB
[    0.000000] OF: reserved mem: initialized node cvu-c7-memory@aa100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000af000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node cvu2-c7-dma-memory@af000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000af100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node cvu2-c7-memory@af100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node slave_cores_region, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000008c0000000, size 512 MiB
[    0.000000] OF: reserved mem: initialized node memtest_region@880000000, compatible id shared-dma-pool
[    0.000000] NUMA: No NUMA configuration found
[    0.000000] NUMA: Faking a node at [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] NUMA: NODE_DATA [mem 0x8ffa98b00-0x8ffa9afff]
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x0000000096ffffff]
[    0.000000]   node   0: [mem 0x0000000097000000-0x0000000097ffffff]
[    0.000000]   node   0: [mem 0x0000000098000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000a0ffffff]
[    0.000000]   node   0: [mem 0x00000000a1000000-0x00000000a1ffffff]
[    0.000000]   node   0: [mem 0x00000000a2000000-0x00000000a5ffffff]
[    0.000000]   node   0: [mem 0x00000000a6000000-0x00000000a60fffff]
[    0.000000]   node   0: [mem 0x00000000a6100000-0x00000000a9b97fff]
[    0.000000]   node   0: [mem 0x00000000a9b99000-0x00000000a9ffffff]
[    0.000000]   node   0: [mem 0x00000000aa000000-0x00000000d9ffffff]
[    0.000000]   node   0: [mem 0x00000000da000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008bfffffff]
[    0.000000]   node   0: [mem 0x00000008c0000000-0x00000008dfffffff]
[    0.000000]   node   0: [mem 0x00000008e0000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] cma: Reserved 32 MiB at 0x00000000fe000000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 23 pages/cpu s56600 r8192 d29416 u94208
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: EL2 vector hardening
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1032191
[    0.000000] Policy zone: Normal
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000 3 root=PARTUUID=c453128a-f306-4dd6-a891-824a35f40b13 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x00000000fa000000-0x00000000fe000000] (64MB)
[    0.000000] BUG: Bad page state in process swapper  pfn:80001
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80001
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] Disabling lock debugging due to kernel taint
[    0.000000] BUG: Bad page state in process swapper  pfn:80002
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80002
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80003
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80003
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80015
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80016
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80016
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80017
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80017
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80018
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80018
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_bac0000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80031
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80031
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80032
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80032
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80033
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80033
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] raw: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    0.000000] page dumped because: nonzero mapcount
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G    B             5.10.120-g889d3a89cbe8-dirty #1
[    0.000000] Hardware name: CUSTOM 4G (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0x0/0x1a0
[    0.000000]  show_stack+0x18/0x68
[    0.000000]  dump_stack+0xd0/0x12c
[    0.000000]  bad_page+0xdc/0x108
[    0.000000]  check_free_page_bad+0x7c/0x88
[    0.000000]  __free_pages_ok+0x3d4/0x3e8
[    0.000000]  __free_pages_core+0xbc/0xd0
[    0.000000]  memblock_free_pages+0x14/0x20
[    0.000000]  memblock_free_all+0x16c/0x24c
[    0.000000]  mem_init+0x4c/0x60
[    0.000000]  start_kernel+0x290/0x4c8
[    0.000000] BUG: Bad page state in process swapper  pfn:80034
[    0.000000] page:(____ptrval____) refcount:0 mapcount:1 mapping:0000000000000000 index:0x0 pfn:0x80034
[    0.000000] flags: 0x0()
[    0.000000] raw: 0000
                        [    0.682203] cma: cma_alloc: alloc failed, req-size: 8 pages, ret: -16
[    0.793538] cma: cma_alloc: alloc failed, req-size: 4 pages, ret: -16
[    1.009269] cma: cma_alloc: alloc failed, req-size: 2 pages, ret: -16
[    1.433707] cma: cma_alloc: alloc failed, req-size: 1 pages, ret: -16
[    1.440352] DMA: failed to allocate 308 KiB GFP_KERNEL|GFP_DMA pool for atomic allocation
[    1.452260] cma: cma_alloc: alloc failed, req-size: 128 pages, ret: -16
[    1.465862] cma: cma_alloc: alloc failed, req-size: 64 pages, ret: -16
[    1.485885] cma: cma_alloc: alloc failed, req-size: 32 pages, ret: -16
[    1.518974] cma: cma_alloc: alloc failed, req-size: 16 pages, ret: -16
[    1.578166] cma: cma_alloc: alloc failed, req-size: 8 pages, ret: -16
[    1.689444] cma: cma_alloc: alloc failed, req-size: 4 pages, ret: -16
[    1.905037] cma: cma_alloc: alloc failed, req-size: 2 pages, ret: -16
[    2.329314] cma: cma_alloc: alloc failed, req-size: 1 pages, ret: -16
[    2.335955] DMA: failed to allocate 308 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocation
[    2.344529] audit: initializing netlink subsys (disabled)
[    2.350192] audit: type=2000 audit(1.960:1): state=initialized audit_enabled=0 res=1
[    2.350784] thermal_sys: Registered thermal governor 'step_wise'
[    2.358120] thermal_sys: Registered thermal governor 'power_allocator'
[    2.364341] cpuidle: using governor menu
[    2.375163] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    2.382130] ASID allocator initialised with 65536 entries
[    2.388272] Serial: AMBA PL011 UART driver
[    2.412210] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    2.419070] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    2.425917] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    2.432764] HugeTLB retel(R) PRO/1000 Network Driver
[    2.898920] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    2.904988] igb: Intel(R) Gigabit Ethernet Network Driver
[    2.910502] igb: Copyright (c) 2007-2014 Intel Corporation.
[    2.916209] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    2.922611] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    2.928863] sky2: driver version 1.30
[    2.933360] VFIO - User Level meta-driver version: 0.3
[    2.939757] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.946455] ehci-pci: EHCI PCI platform driver
[    2.951019] ehci-platform: EHCI generic platform driver
[    2.956444] ehci-orion: EHCI orion driver
[    2.960600] ehci-exynos: EHCI Exynos driver
[    2.964923] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    2.971254] ohci-pci: OHCI PCI platform driver
[    2.975811] ohci-platform: OHCI generic platform driver
[    2.981219] ohci-exynos: OHCI Exynos driver
[    2.985769] usbcore: registered new interface driver usb-storage
[    2.993368] i2c /dev entries driver
[    3.000318] sdhci: Secure Digital Host Controller Interface driver
[    3.006659] sdhci: Copyright(c) Pierre Ossman
[    3.011487] Synopsys Designware Multimedia Card Interface Driver
[    3.018198] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.024874] ledtrig-cpu: registered to indicate activity on CPUs
[    3.031593] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    3.038532] usbcore: registered new interface driver usbhid
[    3.044235] usbhid: USB HID core driver
[    3.050256] optee: probing for conduit method.
[    3.054813] optee: revision 3.17 (15a746d2)
[    3.054970] optee: dynamic shared memory is enabled
E/TC:0 0 std_entry_with_parg:234 Bad arg address 0x8e12e5000
[    3.069789] optee: initialized driver
[    3.074811] NET: Registered protocol family 17
[    3.079453] 9pnet: Installing 9P2000 support
[    3.083854] Key type dns_resolver registered
[    3.088433] registered taskstats version 1
[    3.092627] Loading compiled-in X.509 certificates
[    3.105143] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    3.111984] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    3.122927] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
[    3.153281] omap_i2c 42120000.i2c: bus 0 rev0.12 at 100 kHz
[    3.159341] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 125 domain created
[    3.167987] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 148 domain cr: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    4.973684] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    4.995736] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    5.012096] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    5.247867] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    5.287434] systemd[1]: Mounting Temporary Directory (/tmp)...
         Mounting Temporary Directory (/tmp)...
[    5.305731] systemd1]: Starting udev Coldplug all Devices...
         Starting udev Coldplug all Devices...
[    5.444513] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    5.457995] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Mounted Huge Pages File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory (/tmp).
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[  OK  ] Started Remount Root and Kernel File Systems.
[    5.591885] urandom_read_iter: 37 c8;5;185mDEPEND] Dependency failed for NFS server and services.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Flush Journal to Persistent Storage.
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Started Create Static Device Nodes in /dev.
[  OK  ] Reached target Local File Systems (Pre).
         Mounting /media/ram
                            [    6.622152] urandom_read_iter: 20 callbacks suppressed
[    6.622156] random: systemd: uninitialized urandom read (16 bytes read)
[    6.643654] random: systemd: uninitialized urandom read (16 bytes read)
[    6.655365] random: systemd: uninitialized
                                             [  OK  ] Found device /dev/mmcblk0p1.
         Starting File System Check on /dev/mmcblk0p1...
[  OK  ] Started File System Check on /dev/mmcblk0p1.
         Mounting /tiboot...
[  OK  ] Mounted /tiboot.
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started Create Volatile Files and Directories.
         Starting Network Time Synchronization...
         Starting Update UTMP awn...
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Set.
[  OK  ] Reached target System Time Synchronized.
[    7.648268] urandom_read_iter: 52 callbacks suppressed
[    7.648273] random: systemd: uninitialized urandom read (16 bytes read)
[  OK  ] Started udev Wait for Complete Device Initialization.
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[    7.813506] random: crng init done
[    7.816902] random: 35 urandom warning(s) missed due to ratelimiting
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timers.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting sshd.socket.
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Listening on sshd.socket.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target.
[  OK  ] Started Job spooling tools.
         Starting Load remote core firmwares (remoteproc)...
[  OK  ] Started Periodic Command Scheduler.
[  OK  ] Started D-Bus System 0m.
[  OK  ] Started Runs fast development update daemon.
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
         Starting rc.pvr.service...
[  OK  ] Started System Logging Service.
         Starting Login Service...
[  OK  ] Started IPv6 Packet Filtering Framework.
[  OK  ] Started IPv4 Packet Filework.
[  OK  ] Started rc.pvr.service.
[  OK  ] Reached target Network (Pre).
         Starting Network Service...
[  OK  ] Started Login Service.
[  OK  ] Started Network Service.
         Starting Wait for Network to be Configured...
         Starting Network Name Resolution...
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Network.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Avahi mDNS/DNS-SD Stack...
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
[  OK  ] Started Respond to IPv6 Node Information Queries.
[  OK  ] Started Network Router Discovery Daemon.
         Starting Permit User Sessions...
[  OK  ] Started Xineent For Inetd.
[  OK  ] Started LinuxPTP daemon: phc2sys.
[  OK  ] Started LinuxPTP daemon: ptp4l (IEEE 1588).
[  OK  ] Started Permit User Sessions.
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[FAILED] Failed to start Synchronize em and HW clocks.
See 'systemctl status sync-clocks.service' for details.

CUSTOM login: