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EVM schematic

Mahesh Shinde
Intellectual 270 points

Hello,

In the EVM schematic (Rev E) on the DDR section, what we observe is that the data lines between DDR3 Memory chips and DDR controller are not sequential.

e.g. MEM00_DO of U52 is connected to DDR0_D4 of DDR controller (U31-3).

Could you please urgently let us know the reasons for this?

I have not received response from TI Guys to my previous two post with different subject, I hope I get response for this at the earliest.

 

Best Regards,

Mahesh Shinde

  • 0
    TI__Mastermind 43875 points

    Mahesh,

    The data lines do not typically need to align and can be 'swizzled' to help make routing simpler.

    You cannot do this on the address lines since they are used for commands, but the data lines are position agnostic.

    In the past, many memory manufacturers did not even include bit position numbers on their data lines for this reason.

    BR,

    Steve