DM648 VICP and Video capture port crash problem

Hi Edmond,

It could be one of the following 2 reasons:

- Conflict between the EDMA resources allocated by the VICP and the DSP for the video capture ports. Please refer to http://processors.wiki.ti.com/index.php/VICPLIB_DM644x_DM64x_FAQ on how to make sure there is no such conflicts. Or refer to the user guide http://focus.ti.com/lit/ug/sprugj3e/sprugj3e.pdf, chapter 1.6 .

- Deadlock issue described in errata http://focus.ti.com/lit/er/sprz263f/sprz263f.pdf . Please refer to the user guide http://focus.ti.com/lit/ug/sprugj3e/sprugj3e.pdf,  paragraph 1.6.2 on how to avoid this issue.

regards,

Victor

Dear Victor,

Thank you your advise.

We have double checked that the EDMA channel config on 'bios_edma3_drv_sample_dm648_cfg.c' and 'vicp_edma3_dm648_cfg.c' doesn't have conflict. 

Secondly, for the DM647/DM648 Deadlock Issue handle, we also checked that the 

VICP_EDMA3_TO_DDR_queue = 2
 VICP_EDMA3_FROM_DDR_queue= 3

is correct in our DSP. 

However, the problem is still come out.and always looping in 'edma3CCErrHandler'. 

Is it possible to send the 'bios_edma3_drv_sample_dm648_cfg.c' and 'vicp_edma3_dm648_cfg.c' files to you to check if our config have any error?

Best Regards,

Edmond

Hi Edmond,

Yes, you can have a look at these config files. I have also attached the same files that were extracted from a project that uses both VICP and video inputs. May be these can help you as well.

regards,

Victor0083.affineTransformLive.zip

Sorry, I meant I can look at the config files you are going to send me.

You can also download a demo package that exercices the VICP and video ports from this link:

0434.affineTransformLive.zip

Dear Victor,

I have attached the 2 configure file for the EDMA on DSP BIOS and VICP.

Since we ddn't use Video port 4 on DM648, but using I2C in our project. So I have changed it from the default configure provided by TI.

Please find it from the below link:

0020.edma3_dm648_cfg.zip

By the way, we have studied the deadlock issue: Advisory 1.1.5 as mentioned on the VICP user guide. It said that it caused by the "SDMA/IDMA stalls", and there is a solution by make the whole L2 internal RAM as cache.

We have also try this method, however, we still got the same problem. Does it means our problem doesn't caused by it?

Best Regards,

Edmond

Hello Edmond,

After inspection of your config files, I didn't notice anything wrong so unfortunately I don't have an answer on why you are getting stuck in the error handler. However I don't think it is related to the deadlock issue. Usually the deadlock issue will cause the CPU to lock up, not to be spinning inside an error interrupt handler.

The fact that your system was able to catch an EDMA error can help you to identify the root cause. Please refer to section 2.9.4 of the sprue23d.pdf at http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=sprue23d

regards,

Victor

Dear Victor,

Thank you your advise.

We have actually checked the EDMA ERR register as following result:

EMR: 0x1C00 0000

EMRH: 0x0000 0000

CCERR: 0x0000 0008

ER: 0x1C00 0382

ERH: 0x0000 3000

ESR / ESRH: 0x0000 0000

CER: 0x0000 0000

CERH: 0x0020 0000

From the about result, we find there are missing event error (EMR) on Channel 26, 27, 28 which is VP1 (we used it as video display port). Also the CCERR shows Queue 3 watermark/threshold exceeded.

This error only happen, after we use VICP and config VP2 as Capture port. at the same time.

May I know what is the possible reason for the event miss been happened on video display port?

Best Regards,

Edmond