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USB init code for C6745

Hi, could anybody try to config C6745 USB without BIOS? I use USB 2.0 User´s  Guide as a reference but the USB init code is not working. It locks on a loop waiting USB clock is ok, but it never ends it.

My board uses a 20MHz crystal to generate the clock and USB uses its as ACLK signal.

The config init code is:

void USBInit(void)
{
    Uint16 I;
    volatile Uint32 value =0;

    CSL_SyscfgRegsOvly BootCfg = (CSL_SyscfgRegsOvly)(CSL_SYSCFG_0_REGS);

    BootCfg->KICK0R = 0x83e70b13; // Write Access Key 0
    BootCfg->KICK1R = 0x95A4F1E0; // Write Access Key 1
   
    // Reset the USB controller:
    usbRegs->CTRLR |= 0x00000001;
    //Wait until controller is finished with Reset. When done, it will clear the RESET bit field.
    while ((usbRegs->CTRLR & 0x1) == 1);
    BootCfg->CFGCHIP2 |= 0x1 << 11;        //AUXCLK = USB 2.0 PHY
    BootCfg->CFGCHIP2 |= 0x08;            //Fin = 20MHz       

    // RESET: Hold PHY in Reset
    BootCfg->CFGCHIP2 |= 0x00008000; // Hold PHY in Reset
    // Drive Reset for few clock cycles
    for (I=0; I < 50; I++);
    // RESET: Release PHY from Reset
    BootCfg->CFGCHIP2 &= 0xFFFF7FFF; // Release PHY from Reset
    /* Configure PHY with the Desired Operation */
    // OTGMODE
    BootCfg->CFGCHIP2 &= 0xFFFF9FFF; // 00= > Do Not Override PHY Values
    // PHYPWDN
    BootCfg->CFGCHIP2 &= 0xFFFFFBFF; // 1/0 => PowerdDown/ NormalOperation
    // OTGPWRDN
    BootCfg->CFGCHIP2 &= 0xFFFFFDFF; // 1/0 => PowerDown/ NormalOperation
    // DATAPOL
    BootCfg->CFGCHIP2 |= 0x00000100; // 1/0 => Normal/ Reversed
    // SESNDEN
    BootCfg->CFGCHIP2 &= ~0x00000020; // 1/0 => NormalOperation/ SessionEnd
    // VBDTCTEN
    BootCfg->CFGCHIP2 &= ~0x00000010; // 1/0 => VBUS Comparator Enable/ Disable
    /* Configure PHY PLL use and Select Source */
    // REF_FREQ[3:0]
    // USB2PHYCLKMUX: Select internal Source
    BootCfg->CFGCHIP2 |= 0x00000800; // 1/0 => Internal/External(Pin)

    // PHY_PLLON: On Simulation PHY PLL is OFF
    BootCfg->CFGCHIP2 |= 0x00000040; // 1/0 => On/ Off

    //Mode = Force Device Mode
    BootCfg->CFGCHIP2 |= 0x00004000;   

    /* Wait Until PHY Clock is Good */
        while((BootCfg->CFGCHIP2 & 0x00020000)==0);

 

.....


  • Hi

    Please verify the usb phy input clock frequency is selected properly from the following values.

    Select input Clock Frequency:
    0000 - selectable
    0001 –12MHz
    0010 – 24MHz
    0011 – 48MHz
    0100 – 19.2MHz
    0101 – 38.4MHz
    0110 – 13MHz
    0111 – 26MHz
    1000 – 20MHz
    1001 - 40MHz

    Please try the following sequence to lock USB phy. Note that value 0010 (24Mhz) is selected as usbphy ref input.

     

     

        unsigned int word = 0;
        CFGCHIP2 = 0x09F2;  //value 24Mhz (0010) is selected as usb phy input clock input
        word = CFGCHIP2;
        word |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 11);
        word &= ~((3 << 13));
        CFGCHIP2 = word
        while (!(CFGCHIP2 & (1 << 17)))

    Regards

    Ravibabu

  • Hi Ravibabu.

    Yes, the input clock is selected ok (20MHz). I tried the code you post but it not locked. The line "while(!(CFGCHIP2 & (1<<17)))" is right? In USB User Guide, bit 17 is set when the usb phy is good.

    One of my guess is USBDRVBUS beacuse the in C6745 PTP package it not exist. So, i disable it on CFGCHIP2. Am I right?

    Regards

    Ana Leticia

  •  

    Hi

     I think you are using the AUX_CLK (20MHz),  you need to configure the CFGCHIP2 to select AUX_CLK . Please refer bit 11 of CFGCHIP2 -USB2PHYCLKMUX. The code reference provided uses the internally generated clock.

    Regards

    Ravibabu

     

  • Hi Ravi,

    I´m back to work and trying again to get an USB communication. Now, I get USB interrupt, but I receive several RESET usb command (4 commands) and after that a SUSPEND command. I believe I´m not put EP0 into IDLE mode to get a SETUP packet from host (PC) as I should do after a receive a reset command. Do you have any suggestion to tell me to test here? I tried to set DATAEND bit into PERI_RXCSR register. Any idea? Thanks

  • Hi

    After one or reset from host, host will send the setup packet to device. To receive the setup packet from host, the endpoint-0 must be configured properly to receive the data, particularly check ep0-fifo configuration and enable the ep0-interrupt.  when host send the setup packet , ep0-interrupt will be generated. From this point the ep0-states (IDLE, TXSTATE, RXSTATE) will be used to process the control endpoint request from the host (zero data request, read request or write request). Since the there is no response from the device to the setup packet sent by host , host  SUSPENDs the bus after few trials.

    Regards

    Ravi B

  • Ana,

    I am working on a board that sounds very similar to yours. I am using 20MHz as the AUX clock input to USB. I have not been able to get the Phy to lock and was wondering what you did to correct the problem you were seeing. I have tried several settings of the CFGCHIP2 register and seem unable to get anywhere.

    Would you be willing to post your initialization code, that got the USB Phy PLL locked and running?

     

    David

  • Hi

    If you are using the AUX_CLK (20MHz),  you need to configure the CFGCHIP2 to select AUX_CLK . Please refer bit 11 of CFGCHIP2 -USB2PHYCLKMUX.

    Regards

    Ravi B 

  • Ravi,

    Thanks for the input.

    I found the problem to be a PC board issue. We have corrected the problem and are on to the next step of getting through enumeration.

     

    David

  • Hi Ravi/David,

    I am also facing the same problem with my board.

    Am using AUX_CLK (with a 24Mhz crystal).

    Have set the desired bits in CHIPCFG2 to select AUX clock and provide 24Mhz clock, but still the PLL does not lock.

    @David: Can you please explain the issue you found with your board?

     

    One thing that i could not find in the documentation was the memory mapped address of the PLLC registers, so am not able to find out whether AUXCLK is ON or OFF.

    I hope its ON by default.

     

    Regards

    Manik