Hi,
I´m using the C6747 (DSP BIOS 5.33.05, CGT v6.1.10) on an EVM-board and have a question regarding the PRD timer set up in DSP BIOS. The Clock Manager is used to drive the PRD module. The Clock Manager has the following settings:
Object Memory: IRAM, Timer Selection: Timer 0, Use high resolution time for internal timings: Yes, Eneble High Resolution Timer: Yes, Specify input clock rate: Yes (24MHz), Reset Timer and Time mode: Yes (32-bit unchained), Directly configure on-chip timer registers: Yes (PRD Register: 1000).
These settings give me a time resolution of 41.6us which will be good enough for my application but also a CPU load of 100% which is not desirable. If I increase the PRD setting to 10000 instead of 1000 I get a time resolution of 416us and a CPU load of 15%.
It would be nice to be able to use the higher time resolution so the qusteion is if I´m missing something in the set up or do the BIOS actually use all the "CPU-power" for scheduling the higher time resolution?