I have been using a OMAP L-137EVM. The ref osc is 24 MHz. DSP/BIOS programs the PLL settings to get SYSCLOCK1 to 300 MHz. I examined the registers and it does this by setting the mult to 25 and the post_divide to 2. e.g. 24 x 25 / 2 = 300.
We now have real prototype boards and the ref osc is 19.2 MHz. So I need to change the PLL mult value to 31. Can this be configured with BIOS - in the tconf file? Or do I manually have to reconfigure the PLL registers?
thanks,
Mike