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Problem With ACPY3



I have some problems with ACPY3

I want to copy memory through EDMA(ACPY3 Interface) on DSP/BIOS of DM6467

I copy a big memory with "one" dma, and the cost is TIME0.

I think the these "copy" operation should be "parallel" through DMA, so I divided the memory into 16 sections, and copy them with 16 DMAs, I think the cost should be TIME0/16.

Out of my expectation, the real result of the test is TIME0 !

I have checked my codes, the "transferPending" is false, and my code as following:

for(i = 0 ; i < 16 ; i ++)

{

         ACPY3_start(dmaHandle[i]);

 

 

In additionally, the DMA operation and CPU operation should be parallel, so I take another test : execute memcpy during DMA operation.

my codes as following:

ACPY3_start(dmaHandle) ; //start copy memory1

memcpy(.....) ; //copy memory2

 ACPY3_wait(dmaHandle) ;

I have count the cost for DMA copy and memcpy for two different memory respectly:

Suppose cost of DMA copy Is TIME0

Suppose cost of memcpy is TIME1

If DMA copy and memcpy is "parallel", the result should be MAX(TIME0, TIME1). But the real result of test is TIME0 + TIME1.

Note:

My copy operation is running on DSP side, and my statistics of cost is taken on ARM side.

My DVSDK version is 2_00_00_22

My Framework_Components  version is 2_23_01

My DSP/BIOS version is 5_33_03

Is there any person would tell me the reason?

 

for(i = 0 ; i < 16 ; i ++)

{

         ACPY3_wait(dmaHandle[i]);

  • Shaquille Wu said:

    I have some problems with ACPY3

    I want to copy memory through EDMA(ACPY3 Interface) on DSP/BIOS of DM6467

    I copy a big memory with "one" dma, and the cost is TIME0.

     

    How big is the memory you are copying ?

     

    I think the these "copy" operation should be "parallel" through DMA, so I divided the memory into 16 sections, and copy them with 16 DMAs, I think the cost should be TIME0/16.

    Out of my expectation, the real result of the test is TIME0 !

    I have checked my codes, the "transferPending" is false, and my code as following:

    for(i = 0 ; i < 16 ; i ++)

    {

             ACPY3_start(dmaHandle[i]);

     

    How many QDMA channels have you configured for DMAN3 ? That amount of parallelism also depends on the number of individual QDMA channels you use, and the different TCs that get engaged for use etc. 

     

    In additionally, the DMA operation and CPU operation should be parallel, so I take another test : execute memcpy during DMA operation.

    my codes as following:

    ACPY3_start(dmaHandle) ; //start copy memory1

    memcpy(.....) ; //copy memory2

     ACPY3_wait(dmaHandle) ;

    I have count the cost for DMA copy and memcpy for two different memory respectly:

    Suppose cost of DMA copy Is TIME0

    Suppose cost of memcpy is TIME1

    If DMA copy and memcpy is "parallel", the result should be MAX(TIME0, TIME1). But the real result of test is TIME0 + TIME1.

    Note:

    My copy operation is running on DSP side, and my statistics of cost is taken on ARM side.

     

    How are you measuring the time cost ? 


    My DVSDK version is 2_00_00_22

    My Framework_Components  version is 2_23_01

    My DSP/BIOS version is 5_33_03

    Is there any person would tell me the reason?

     

     

    for(i = 0 ; i < 16 ; i ++)

    {

             ACPY3_wait(dmaHandle[i]);

     

  • Thanks for your answer very much at first, Gunjan

    1.My memory size is 1600*1200*2 bytes

    2.I know that the max number of hardware qdma is 8 channels, so I have also taken another test that copy the memory by 8 section with 8 qdma. the result is still TIME0, not TIME0/8. I configured the number of channel through ACPY3's interface. In other words, I configured them in "dmaGetChannels", my codes as following :

    /*
     *  ======== FASTCOPY_UN_dmaGetChannelCnt ========
     *  Return max number of logical channels requested.
     */
    Uns FASTCOPY_UN_dmaGetChannelCnt(Void)
    {
        GT_0trace(curTrace, GT_ENTER, "FASTCOPY_UN_dmaGetChannelCnt()\n") ;

        return (NUM_FCDMA_CH) ;
    }


    /*
     *  ======== FASTCOPY_UN_dmaGetChannels ========
     *  Declare DMA resource requirement/holdings.
     */
    Uns FASTCOPY_UN_dmaGetChannels(IALG_Handle handle, IDMA3_ChannelRec dmaTab[])
    {
        FASTCOPY_UN_Obj* pFCObj = (Void *)handle ;
        int i = 0 ;

        GT_2trace(curTrace, GT_ENTER,
            "FASTCOPY_UN_dmaGetChannels(0x%x, 0x%x)\n", handle, dmaTab);

        for (i = 0 ; i < NUM_FCDMA_CH ; i++)
        {
     dmaTab[i].handle = pFCObj->dmaHandle[i] ;
         //GT_2trace(curTrace, GT_ENTER, "dmaTab[%d] = %x\n", i, dmaTab[i].handle);
         dmaTab[i].numTransfers = 1 ;
         dmaTab[i].numWaits = 1 ;
            dmaTab[i].priority = IDMA3_PRIORITY_LOW ;
            dmaTab[i].persistent = FALSE ;
            dmaTab[i].protocol = &ACPY3_PROTOCOL ;
        }

        return (NUM_FCDMA_CH) ;
    }

    /*
     *  ======== FASTCOPY_UN_dmaInit ========
     *  Initialize instance object with granted logical channel.
     */
    Int FASTCOPY_UN_dmaInit(IALG_Handle handle, IDMA3_ChannelRec dmaTab[])
    {
        FASTCOPY_UN_Obj* pFCObj = (Void *)handle ;

     int i = 0 ;

        GT_2trace(curTrace, GT_ENTER, "FASTCOPY_UN_dmaInit(0x%x, 0x%x)\n",
            handle, dmaTab);

     for (i = 0 ; i < NUM_FCDMA_CH ; i++)
     {
          pFCObj->dmaHandle[i] = dmaTab[i].handle ;
      //GT_2trace(curTrace, GT_ENTER, "dmaTab[%d] = %x\n", i, dmaTab[i].handle);
     }
        return (IALG_EOK) ;
    }


    /*
     *  ======== FASTCOPY_UN_IDMA3 ========
     *  This structure defines TI's implementation of the IDMA3 interface
     *  for the FASTCOPY_UN module.
     */
    IDMA3_Fxns FASTCOPY_UN_IDMA3 = {      /* module_vendor_interface */
        &FASTCOPY_UN_IALG,              /* IALG functions */
        FASTCOPY_UN_dmaChangeChannels,  /* ChangeChannels */
        FASTCOPY_UN_dmaGetChannelCnt,   /* GetChannelCnt */
        FASTCOPY_UN_dmaGetChannels,     /* GetChannels */
        FASTCOPY_UN_dmaInit             /* initialize logical channels */
    };

    the log about the dma allocation(8 channels) generated by CE_DEBUG as following:

    [DSP] @1,221,112tk: [+0 T:0x8ba00724] unic.sdo.codecs.fastcopy - FASTCOPY_UN_dmaInit(0x8ba0c780, 0x8ba11380)
    [DSP] @1,221,173tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 5
    [DSP] @1,221,217tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,221,262tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 96 (Addr 0x1c04c00)
    [DSP] @1,221,310tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,221,353tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 32
    [DSP] @1,221,391tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 6
    [DSP] @1,221,434tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,221,477tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 97 (Addr 0x1c04c20)
    [DSP] @1,221,524tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,221,567tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 33
    [DSP] @1,221,605tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 7
    [DSP] @1,221,648tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,221,691tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 98 (Addr 0x1c04c40)
    [DSP] @1,221,738tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,221,781tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 34
    [DSP] @1,221,819tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 0
    [DSP] @1,221,862tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,221,905tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 99 (Addr 0x1c04c60)
    [DSP] @1,221,952tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,221,995tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 35
    [DSP] @1,222,033tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 1
    [DSP] @1,222,076tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,222,119tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 100 (Addr 0x1c04c80)
    [DSP] @1,222,166tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,222,209tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 36
    [DSP] @1,222,247tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 2
    [DSP] @1,222,290tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,222,334tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 101 (Addr 0x1c04ca0)
    [DSP] @1,222,381tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,222,424tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 37
    [DSP] @1,222,462tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 3
    [DSP] @1,222,505tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,222,548tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 102 (Addr 0x1c04cc0)
    [DSP] @1,222,596tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,222,638tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 38
    [DSP] @1,222,677tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 4
    [DSP] @1,222,720tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,222,763tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 103 (Addr 0x1c04ce0)
    [DSP] @1,222,810tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,222,853tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 39
    [DSP] @1,222,894tk: [+0 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_grantDmaChannels> Exit (status=0)
    [DSP] @1,222,946tk: [+0 T:0x8ba00724] ti.sdo.ce.alg.Algorithm - Algorithm_create> return (0x8fa9bac0)

    My DMAN&EDMA3 configurations in .cfg file as following:

    var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');

     DMAN3.heapInternal    = "L1DHEAP";       /* L1DHEAP is an internal segment */
     DMAN3.heapExternal    = "DDRALGHEAP";
     DMAN3.idma3Internal   = true ;

     DMAN3.paRamBaseIndex     = 96;  // 1st EDMA3 PaRAM set available for DMAN3
     DMAN3.numQdmaChannels    = 8;   // number of device's QDMA channels to use
     DMAN3.qdmaChannels       = [0,1,2,3,4,5,6,7]; // choice of QDMA channels to use
     DMAN3.numPaRamEntries    = 32;  // number of PaRAM sets exclusively used by DMAN
     DMAN3.numPaRamGroup[0]   = 32;  // number of PaRAM sets for scratch group 0
     DMAN3.numTccGroup[0]     = 32;  // number of TCCs assigned to scratch group 0
     DMAN3.tccAllocationMaskL = 0;   // bit mask indicating which TCCs 0..31 to use
     DMAN3.tccAllocationMaskH = 0xffffffff; // assign all TCCs 32..63 for DMAN

        var EDMA3 = xdc.useModule('ti.sdo.fc.edma3.Settings');  
        EDMA3.maxPaRams[0] = 384;
        EDMA3.maxTccs[0] = 49;
        EDMA3.maxEdmaChannels[0] = 49;
        EDMA3.maxQdmaChannels[0] = 0;
        EDMA3.trace = false;
        EDMA3.debug = false;   

        var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');
        EDMA3CHAN.debug = false;
        EDMA3CHAN.trace = false;

    3.I measured the time cost by funtion of "gettimeofday" in ARM(Montavista Linux) side, not in DSP side. We can believe that the result is accurate.

    4.I want to know why the ACPY3 just allocate QDMA ? why not allocate other DMA resource, such as EDMA?I also taked the test through 16 dma, and the log about the dma allocation(16 channels) generated by CE_DEBUG as following:

    [DSP] @1,230,192tk: [+0 T:0x8ba00724] unic.sdo.codecs.fastcopy - FASTCOPY_UN_dmaInit(0x8ba0c780, 0x8ba11380)
    [DSP] @1,230,250tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 5
    [DSP] @1,230,294tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,230,340tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 96 (Addr 0x1c04c00)
    [DSP] @1,230,387tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,230,430tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 32
    [DSP] @1,230,478tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 6
    [DSP] @1,230,521tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,230,564tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 97 (Addr 0x1c04c20)
    [DSP] @1,230,611tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,230,654tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 33
    [DSP] @1,230,692tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 7
    [DSP] @1,230,735tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,230,778tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 98 (Addr 0x1c04c40)
    [DSP] @1,230,825tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,230,868tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 34
    [DSP] @1,230,906tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 0
    [DSP] @1,230,949tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,230,992tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 99 (Addr 0x1c04c60)
    [DSP] @1,231,039tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,231,081tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 35
    [DSP] @1,231,120tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 1
    [DSP] @1,231,162tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,231,206tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 100 (Addr 0x1c04c80)
    [DSP] @1,231,253tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,231,296tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 36
    [DSP] @1,231,334tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 2
    [DSP] @1,231,377tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,231,420tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 101 (Addr 0x1c04ca0)
    [DSP] @1,231,468tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,231,510tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 37
    [DSP] @1,231,549tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 3
    [DSP] @1,231,592tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,231,635tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 102 (Addr 0x1c04cc0)
    [DSP] @1,231,682tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,231,725tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 38
    [DSP] @1,231,763tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 4
    [DSP] @1,231,806tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,231,849tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 103 (Addr 0x1c04ce0)
    [DSP] @1,231,897tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,231,939tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 39
    [DSP] @1,231,978tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 5
    [DSP] @1,232,021tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,232,064tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 104 (Addr 0x1c04d00)
    [DSP] @1,232,111tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,232,153tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 40
    [DSP] @1,232,192tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 6
    [DSP] @1,232,235tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,232,278tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 105 (Addr 0x1c04d20)
    [DSP] @1,232,325tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,232,368tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 41
    [DSP] @1,232,406tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 7
    [DSP] @1,232,449tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,232,492tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 106 (Addr 0x1c04d40)
    [DSP] @1,232,540tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,232,582tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 42
    [DSP] @1,232,621tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 0
    [DSP] @1,232,664tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,232,707tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 107 (Addr 0x1c04d60)
    [DSP] @1,232,755tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,232,800tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 43
    [DSP] @1,232,838tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 1
    [DSP] @1,232,881tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,232,924tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 108 (Addr 0x1c04d80)
    [DSP] @1,232,972tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,233,014tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 44
    [DSP] @1,233,053tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 2
    [DSP] @1,233,095tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,233,138tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 109 (Addr 0x1c04da0)
    [DSP] @1,233,186tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,233,228tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 45
    [DSP] @1,233,267tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 3
    [DSP] @1,233,309tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,233,353tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 110 (Addr 0x1c04dc0)
    [DSP] @1,233,400tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,233,443tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 46
    [DSP] @1,233,481tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Qdma: 4
    [DSP] @1,233,524tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned PaRam(s):
    [DSP] @1,233,567tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 111 (Addr 0x1c04de0)
    [DSP] @1,233,615tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> Assigned Tcc(s):
    [DSP] @1,233,657tk: [+4 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_createChannels> 47
    [DSP] @1,233,701tk: [+0 T:0x8ba00724] ti.sdo.fc.dman3 - DMAN3_grantDmaChannels> Exit (status=0)
    [DSP] @1,233,751tk: [+0 T:0x8ba00724] ti.sdo.ce.alg.Algorithm - Algorithm_create> return (0x8fa9bc80)

     

  • Is there anyone would tell me these reasons?

  • I have requested some people to help analyze your issue. In the meantime, could you try and change the DMAN3 configuration, so each QDMA channel uses a diferent TC, and tell me if you see any change in timing ?

    You can do this by changing the following configuration:-

    DMAN3.qdmaQueueMap = {0,1,2,3,4,5,6,7};

    This maps each qdma channel to a different event queue. You may have to check how many event queues are on your device and perform this mapping accordingly.

  • Thanks for your answer at first,

    I have change the DMAN3 configuration in my .cfg file

    DMAN3.qdmaQueueMap = [0,1,2,3,4,5,6,7];

    Out of my expectation, it is abnormal, it dead !

    I am very confuse, would you give me some further suggestion?

  • In additional, My device is DM6467(729 device).

    How can I know "how many event queues are on my device and perform this mapping accordingly" ?

  • Is there any one encounter my problem?

  • Hi Shaquille

    For your first experiment of  splitting a large transfer of size:s  into N smaller transfers of size: s/N submitted in parallel you should expect some benefits from the extra parallelism that the EDMA traffic controller may be able to exploit, however I would not expect the benefits to be as much as you expected. Ultimately the DDR bandwidth is  your limit and bottleneck. Here it is possible that the EDMA controllers bursting of the data via a single large transfer is just as efficient as transfering the chunks in parallel.

    Similarly for your second experiment of transfering some data using DMA and some using CPU, you may be running into the same type of issue. DDR traffic is your bottleneck. If you were doing some other operations other than CPU issued memcopy (e.g. computation or computing the next set of data to transfer, etc.,) or issuing transfers to/from different memory spaces you should get more benefits from the CPU/DMA parallelism.

    Best regards,

    Murat 

     

     

     

  • Shaquille Wu said:

    In additional, My device is DM6467(729 device).

    How can I know "how many event queues are on my device and perform this mapping accordingly" ?

     

    This information is available in the device data sheet. I found the following information:-

    NUM_EVQUE Number of Event Queues 4

    You can set your DMAN3 configuration to assign each QDMA channel to one of these 4 event queues:-

    DMAN3.qdmaQueueMap = {0,1,2,3,0,1,2,3};

     


  • Thanks for your answer, I will check my datasheet, and will take new experiment as your method.