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Clock Diagram for EVM Board document for TI

Wenjun Huang
Expert 1770 points
Other Parts Discussed in Thread: TMS320C6672, CDCE62005

In the EVM Board document for TI, for the Clock Diagram, it can be seen that the frequency for the various clock input are as follows:

a. core clk: 100MHz
b. SRIO/ SGMII clk: 312.5MHz
c. DDR clk: 66.7MHz
d. PCIe clk: 100MHz
e. Hyperlink: 312.5MHz
f.  PASS: 100MHz

May I know the reason for these frequencies? Is it randomly assigned or is there special frequencies that each clk can take.

  • 0
    TI__Mastermind 30825 points

    There is a lot of flexibility in what frequencies can actually be used, but there's also some limited values that need to be used to support things such as particular bootmodes.

    The BootROM code will setup the IP required for a particular bootmode (you provide the bootmode and some configuration information based on how the bootmode pins are pulled/driven during Power On Reset.)  You probably want to look into chapter 2 of the Data Manual and the Boot Loader User Guide for more details.

    For SRIO, SGMII and Hyperlink 312.5MHz is one of these optional frequencies (Could have used 156.25 or 250MHz for all three of these as well.)

    Core was chosen at 100MHz since 1GHz is a simple multiplication factor and it's also a frequency used by PCIe for boot.  PASS uses it because you want to setup PASS to be around 1/3 of the Core frequency and it's simple to setup and not use another frequency for this.

    DDR3 was choosen to be 66.7MHz as a x10 PLL setting to get to the 1333MHz Transfer Rate (667MHz clock rate) used on the EVM.

    There are other values that could have been used, but this was what was chosen on the EVM.  As you can see it wasn't random, but there is a balance between being flexible and restrictive for boot purposes since the boot ROM code inside the device needs to be able to configure necessary PLLs for the IP that it requires for booting the device.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 1770 points

    I got the reason for SRIO, SGMII, Hyperlink. The pages for these three are p27, 28 and 31. It is possible to choose 156.25, 250 or 312.5 MHz as the input frequencies for these 3 SerDes.

    For PLL clock inputs which include core clock, DDR3 and PASS, the possible input clock frequencies are on p31 and are 50, 66.67, 80, 100, 156.25, 250, 312.5, 122.88 MHz(so weird??).

    There are still some doubts.

    What is the max frequency supported by the C6672? Is it 1GHz, 1.2 GHz (p31) or 1.25 GHz (p11)?

    What is the possible frequency for PCIe, a SerDes clock?

    What is the difference between a PLL and a SerDes clock?

    Why PASS needs to be around 1/3 of Core frequency?

    What do you mean by IP?

  • 0 in reply to Wenjun Huang
    TI__Mastermind 30825 points

    The max frequency of the device is whatever speed grade is purchased.  We primarily support 1GHz and 1.25GHz. The table on page 31 shows the default PLL settings for the speed grade value e-fused into the system, originally we were going to support 1GHz and 1.2GHz.  We're looking at updating the ROM on the next revision to be able to support a 1.25GHz PLL default setting for the given input clocks, currently one would have to reprogram the PLLs to go from the 1.2GHz default to 1.25GHz speed entitlement on a 1.25GHz device.

    The PCIe UG should cover the SerDes clock options for PCIe.

    PLL takes a clock, a SerDes clock is just a clock for that particular SerDes module, it will go to the SerDes modules PLL first which is configured along with all the other SerDes configurations for that module.

    In order for the PASS subsystem performance to keep up w/ the GigE ports on 1GHz it needs to be > 300MHz, w/ 1GHz being the slow speed supported on the devices using the 1/3 ratio for setting up the PLL is the best option.  Operating it at higher speeds isn't going to improve performance and it can operate up to 1/3 of the CPU speed for all speeds supported.

    IP is just short for interface peripheral.   In other words any peripheral that could be used to interface to another devices is referred to as an IP.

    Best Regards,

    Chad

  • 0 in reply to Wenjun Huang
    Expert 1770 points

    It would be great if there is a table of frequencies for the different clk for C66. It would help the hardware designer to design the hardware instead of going through several document. I am referring to literature number SPRS708C (TMS320C6672 data manual) for the following page number.

    clk

    Frequency

    Reason

    CORECLK

    100MHz

    chosen at 100MHz since 1GHz is a simple multiplication factor and it's also a frequency used by PCIe for boot.

    What is the frequency range? Is it 40MHz to 312.5MHz since from p143 of C6672 datasheet, the cycle_time is 3.2ns to 25ns? If I buy a 1GHz device, I can clock it at less than 1GHz, right? Example is I clock CORECLK to be 100MHz but uses x9 multiplier to result in 900MHz for the CorePac.

    SRIOSGMIICLK

    312.5MHz

    156.25, 250MHz, 312.5MHz allowable (p29, 30)

    DDRCLK

    66.7MHz

    66.7MHz as a x10 PLL setting to get to the 1333MHz Transfer Rate (667MHz clock rate) used on the EVM

    PCIECLK

    100MHz

    What is the frequency ranges? I could not find it in the PCIe user guide. What is the reason when you choose 100MHz for the PCIe clock?

    MCMCLK

    312.5MHz

    156.25, 250MHz, 312.5MHz allowable (p33)

    PASSCLK

    100MHz

    setup PASS to be around 1/3 of the Core frequency and it's simple to setup and not use another frequency for this. In order for the PASS subsystem performance to keep up w/ the GigE ports on 1GHz it needs to be > 300MHz, w/ 1GHz being the slow speed supported on the devices using the 1/3 ratio for setting up the PLL is the best option.  Operating it at higher speeds isn't going to improve performance and it can operate up to 1/3 of the CPU speed for all speeds supported. Is there any frequency ranges for this? I could not find the frequency on Packet Accelerator user guide.
  • 0 in reply to Wenjun Huang
    Expert 1770 points

    I would like to use CDCE62005 with differential input clk 100MHz to generate 5 clk output 66.7MHz, 100MHz, 100MHz, 312.5MHz, 25MHz. Is it possible? What is the configuration file for this output?

  • 0 in reply to Wenjun Huang
    TI__Mastermind 30825 points

    Specific clocking requirements should be well defined within the Hardware Design Guidelines for the SerDes based peripherals.  The others have no such requirements.

    The clock CDCE62005 is one of the recommended clocks for generating 5 separate clocks as documented in the Keystone Hardware Design Guidelines.  It should be fully documented how to use, if you need support on using the CDCE62005, you'll want to post on the Clocks and Timers forum, which it appears you have already done so.

    Best Regards,
    Chad