This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Tony,
you should be able to model this for AM62x based on the AM64x DTS entry for main_spi0 that can be found at https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am64-main.dtsi?h=ti-linux-5.10.y#n372:
main_spi0: spi@20100000 { compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; reg = <0x00 0x20100000 0x00 0x400>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 141 0>; dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; dma-names = "tx0", "rx0"; };
So it's about adding the dmas and dma-names properties. Note that for main SPI interfaces other than main_spi0 you'll need to update the PSI-L Source and Destination Thread IDs accordingly. For main_spi0 they happen to be the same for AM62x and AM64x so the above example should apply as-is. For the other main SPI interfaces please refer to the respective table in the TISCI User's Guide at https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/psil_cfg.html. Look for the pdma_main*_mcspi1_rx and pdma_main*_mcspi0_tx entries and update your DTS node accordingly.
Regards, Andreas