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(6748,USB2.0) Is there a DELAY between INT tx Dma and EP.tx_package_ready?

twicave Feng
Intellectual 850 points

I have a question about 6748's USB2.0 peripheral.

 

[ USB worked in HOST mode. and DMA is actived ]

I started an EP_OUT operation, When the last Tx DMA triggered (the entired tx transfer will splitted into several stages), In ISR, I wait untile HOSTTXCSR.tx_package_ready is set to 0, then I started a EP_IN operation.

In most cases,  It works well. But sometimes It hangs up. I checked register's value, found epOut.TXCSR 's value is xx03;

so I guessed there should be a DELAY between DMA queue empty signal and EPOUT.TxPackageReady Bit set to 1.

Is that true?