DDR2 tDelay timing adjustment

Takeshi Yuasa

Dear Sir,

Would you please somebody tell me how to adjust "tDelay" timing (CKE low to CK/CK# off) by DM368 registers?
Right now a CK off and a CKE low is almost simultaneously happened (=0ns).
We should meet JEDEC standard (tDelay min = tIS+tCK(avg)+tIH), so please help us.

We are using DDR2-667 and DDR2-800.

for your reference: DDR2-667(DDR2-800)
tIS = 0.2 (0.175)
tCK(avg) = 3(2.5)
tIH = 0.275(0.25)

tDelay(min) should be 3.475(2.925) ns

Regards,

Takeshi

over 14 years ago

0 Marcus Cooksey over 14 years ago

TI__Genius 9510 points

Please see the timing register in the DDR2 memory controller User Guide section 4.4 and 4.5.

http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprufi2&fileType=pdf

0 Takeshi Yuasa over 14 years ago in reply to Marcus Cooksey

Expert 1230 points

Thanks for your feedback.

However, there is no timing related register fields for the tDelay (CKE low to CK off). There is only one register field related to CKE (t_cke) but it seems not effective parameter for tDelay.

Regards,

Takeshi

0 Marcus Cooksey over 14 years ago in reply to Takeshi Yuasa

TI__Genius 9510 points

Our EMIF does not deassert CKE asynchronously. The CKE output is driven using a flop which clocks on the rising edge of the DDR clock. Therefore, tDelay parameter is not required.

CKE is deasserted/asserted by the EMIF only when entering/exiting self-refresh or power-down modes. In this case, CKE is deasserted/asserted synchronously.

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DDR2 tDelay timing adjustment