Problems with C6713B and SDRAM

Jeremy13304

I am developing a DSPC6713B board with one chip of CPLD. The Timer and general purpose IO programs work normally. The input clock to the DSP CLKIN pin is 25MHz and dsp works on the frequency of 200MHz.

When reset the DSP, the frequency of ECLKOUT,CLKOUT3, CLKOUT2 signal is correct as the datasheet suggets. The frequency of ECLKOUT signal is CLKIN divided by 2 and CLKOUT3,CLKOUT2 is divided by 8. Everything seems perfect.

But SDRAM can't be written. A 32-bit SDRAM with 4 banks is connected to the CE0.THE ECLKOUT signal is set to 80MHz(one fifth of 400MHz) ultilizing the PLL intialization programs. BUT the ECLKOUT signal turns out to be very strange. When Eclkout frequency is about 20MHz, the ECLKOUT signal wave is a sinusoidal with the amplitude of about 3V, the minimum voltage of signal is about 0.4V. As the ECLKOUT frequency increases to 50MHz, it is still a sinusoidal wave, but the amplitude decreases to about 0.4V, the minimum voltage is about 1.2V, that is, there exists more or less a 1.2v DC offset in the ECLKOUT signal.

The dsp core supply voltage maintains at the level of 1.19V. It is the same for the ECLKOUT signal if I seperated the DSP and SDRAM. BTW, the signal is tested by a oscilloscope with bandwidth of 60MHz(200MSa/s). There are no differences for the ECLKOUT signal with a different oscilloscope with bandwidth of 100MHz(200MSa/s).

Any suggestion would be greated appreciated~~~~

over 16 years ago

0 TimHarron over 16 years ago

TI__Mastermind 18130 points

I can't say that I have ever seen this behavior coming out of this chip. I think in another thread of yours someone posted an idea that your scope was not sampling the input (ECLKOUT) fast enough to get an accurate reading and I think that is still the case here. In order to capture a sine wave the sample rate must be at LEAST two times the frequency - and the more the better. So where a 100MHz scope would not properly capture the 80MHz input something like a 500MHz scope would work perfectly.

Now with that said if you are able to confirm that accesses to SDRAM are failing at this frequency then the speed of the scope is irrelevant. But without knowing more about the board such as which memory you are using, how far the traces are between DSP and SDRAM, and so on I cannot really comment on why this might fail at higher speeds.

0 Jeremy13304 over 16 years ago in reply to TimHarron

Intellectual 450 points

3x very much for your patient explaination and reply! The SDRAM on my board is MT48LC4M32B2 which is a chip with 32-bit, 4 banks with each bank 1M. The SDRAM is mapped into the CEO EMIF space. I am sure the hardware connection is correct. What do you mean about the trace between DSP and SDRAM, the ECLKOUT signal or XD[31..0] or XA[21..2]? The ECLKOUT signal from DSP is connnected to SDRAM Clock through a termination resistor with 33 ohm. The length of the ECLKOUT trace between DSP and the termination resistor is about 211.42 MIL(5mm), the resistor output to the SDRAM clock input is about 1170MIL(29mm).

The SDRAM is mapped into the CEO space in the GEL file as follows:

GEL_MapAdd(0x80000000,0,0x08000000,1,1); /* CE0, SDRAM, 128 MBytes */

The EMIF initialization program related to SDRAM is as follows:

  /*Global control register*/
  0x00003060        |
  EMIF_FMKS(GBLCTL,NOHOLD,DISABLE)  |
  EMIF_FMKS(GBLCTL,EKEN,DEFAULT)  |
  EMIF_FMKS(GBLCTL,CLK1EN,DISABLE) |
  EMIF_FMKS(GBLCTL,CLK2EN,DISABLE),

  /*CE0 space control register, SDRAM,MTYPE = SDRAM32
  the remaining register fileds have no effect*/
  EMIF_FMKS(CECTL,WRSETUP,DEFAULT) |
  EMIF_FMKS(CECTL,WRSTRB,DEFAULT)  |
  EMIF_FMKS(CECTL,WRHLD,DEFAULT)  |
  EMIF_FMKS(CECTL,RDSETUP,DEFAULT) |
  EMIF_FMKS(CECTL,TA,OF(2))   |
  EMIF_FMKS(CECTL,RDSTRB,DEFAULT)  |
  EMIF_FMKS(CECTL,MTYPE,SDRAM32)  |
  EMIF_FMKS(CECTL,RDHLD,DEFAULT),

    /* SDRAM control */
   EMIF_FMKS(SDCTL,SDBSZ,4BANKS)  |
    EMIF_FMKS(SDCTL,SDRSZ,12ROW)  |
    EMIF_FMKS(SDCTL,SDCSZ,8COL)   |
    EMIF_FMKS(SDCTL,RFEN,ENABLE)  |
    EMIF_FMKS(SDCTL,INIT,YES)   |
    EMIF_FMKS(SDCTL,TRCD,OF(2))   |
    EMIF_FMKS(SDCTL,TRP,OF(2))   |
    EMIF_FMKS(SDCTL,TRC,OF(7)),

        /*SDRAM Time control*/
        EMIF_FMKS(SDTIM,XRFR,OF(1))   |
        EMIF_FMKS(SDTIM, CNTR, OF(0))       |
        EMIF_FMKS(SDTIM, PERIOD, OF(4096)),

        /*SDRAM extension control register*/
  EMIF_FMKS(SDEXT, WR2RD, OF(0))      |
        EMIF_FMKS(SDEXT, WR2DEAC, OF(2))    |
        EMIF_FMKS(SDEXT, WR2WR, OF(0))      |
        EMIF_FMKS(SDEXT, R2WDQM, OF(1))     |
        EMIF_FMKS(SDEXT, RD2WR, OF(4))      |
        EMIF_FMKS(SDEXT, RD2DEAC, OF(1))    |
        EMIF_FMKS(SDEXT, RD2RD, OF(0))      |
        EMIF_FMKS(SDEXT, THZP, OF(2))       |
        EMIF_FMKS(SDEXT, TWR, OF(2))        |
        EMIF_FMKS(SDEXT, TRRD, OF(0))       |
        EMIF_FMKS(SDEXT, TRAS, OF(5))       |
        EMIF_FMKS(SDEXT, TCL, OF(1))

Any suggestion would be appreciated~~~

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Problems with C6713B and SDRAM