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TDA4VM: how to config the PCIe to support 64bits prefetch memory

yinli liang
Prodigy 50 points
Part Number: TDA4VM

Hi TI, 

From spec, TDA4VM PCIe1 have a 4GB 64bit prefetch memory:

/* PCIe1 DAT0 has 128MB available and is used for configuration space,
* io space and 32-bit prefetch and non-prefetch memory
* 0x00 18000000 - 0x00 18000FFF 4KB, configuration space
* 0x00 19000000 - 0x00 19FFFFFF 16MB, io space
* 0x00 1A000000 - 0x00 1BFFFFFF 32MB, 32-bit prefetch
* 0x00 1C000000 - 0x00 1FFFFFFF 64MB, 32-bit non-prefetch
* PCIe1 DAT1 has 4GB available and is used for 64-bit prefetch memory
* 0x41 00000000 - 0x41 FFFFFFFF
*/

From the k3-j721e-main.dtsi, I found the config for pcie1_rc is：

pcie1_rc: pcie@2910000 {
    compatible = "ti,j721e-pcie-host";
    reg = <0x00 0x02910000 0x00 0x1000>,
          <0x00 0x02917000 0x00 0x400>,
          <0x00 0x0d800000 0x00 0x00800000>,
          <0x00 0x18000000 0x00 0x00001000>;
    reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
    interrupt-names = "link_state";
    interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
    device_type = "pci";
    ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
    max-link-speed = <3>;
    num-lanes = <2>;
    power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
    clocks = <&k3_clks 240 1>;
    clock-names = "fck";
    #address-cells = <3>;
    #size-cells = <2>;
    bus-range = <0x0 0xff>;
    vendor-id = <0x104c>;
    device-id = <0xb00d>;
    msi-map = <0x0 &gic_its 0x10000 0x10000>;
    dma-coherent;
    ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
         <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
    dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};

If I have to support one memory space for 32-bit non-prefetch, and have two other spaces available for 32-bit prefetch and 64-bit prefetch.

how to config the ranges, this is my setting, is it right?

 ranges =<0x01000000 0x0 0x19000000 0x0 0x19000000 0x0 0x01000000>;   /* io */

<0x42000000 0x0 0x1A000000 0x0 0x1A000000 0x0 0x02000000>,   /* 32-bit prefetchable */ 

<0x02000000 0x0 0x1C000000 0x0 0x1C000000 0x0 0x04000000>,    /* 32-bit non-prefetchable */ 

<0x43000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>, /* 64-bit prefetchable */ 

and also, I also add code to parse the range for  32-bit prefetch and 64-bit prefetch,  how should I config other PCIe registers to support my requirement.

e.g. in the cdns_pcie_host_init_root_port() in the drivers/pci/controller/cadence/pcie-cadence-host.c,  maybe I should update the CDNS_PCIE_LM_RC_BAR_CFG register value, but I am not familiar with it, could you give me some suggestion? and also is there any other functions need to update?

static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
{
    struct cdns_pcie *pcie = &rc->pcie;
    u32 value, ctrl;
    u32 id;

    /*
     * Set the root complex BAR configuration register:
     * - disable both BAR0 and BAR1.
     * - enable Prefetchable Memory Base and Limit registers in type 1
     *   config space (64 bits).
     * - enable IO Base and Limit registers in type 1 config
     *   space (32 bits).
     */
    ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
    value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
        CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
        CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
        CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
        CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
        CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
    cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);

by the way, another question here, why need to disable BAR0 and BAR1 by value=CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) ？

8-6 RCBAR0C R/W 4h Specifies the configuration of RC BAR0.
The various encodings are:
000: Disabled
001: 32bit IO BAR
010-
011: Reserved
100: 32bit memory BAR, non prefetchable
101: 32bit memory BAR, prefetchable
110: 64bit memory BAR, non prefetchable
111: 64bit memory BAR, prefetchable

16-14 RCBAR1C R/W 0h Specifies the configuration of RC BAR1.
The various encodings are:
000: Disabled
001: 32bit IO BAR
010-
011: Reserved
100: 32bit memory BAR, non prefetchable
101: 32bit memory BAR, prefetchable
110-
111: Reserved