• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 540 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How do I setup the GPIO pins and where are they physically on the PADK c6727?

manferd
Prodigy 70 points
Other Parts Discussed in Thread: TMS320C6727

I've been trying to write a simple program for the PADK Professional Audio Development Kit C6727 DSP that will turn on/off an LED using the HAS pin setup as a GPIO pin according to the state of one of the push buttons, but I can't seem to get it right.  Here is what I have:

CSL_UhpiHandle           hUhpi = (CSL_UhpiHandle) NULL;
CSL_UhpiObj              uhpiObj;
CSL_Status               status;

Uint32                   response;

int main()
{
    CSL_chipInit( NULL );
    hUhpi = CSL_uhpiOpen(&uhpiObj,CSL_UHPI,NULL,&status);
    GPIO_Reset();
    CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG);
    CSL_uhpiHwControl (hUhpi, CSL_UHPI_CMD_SET_GPIO_EN, (void *)((Uint32)0x04));
    CSL_uhpiHwControl (hUhpi, CSL_UHPI_CMD_SET_GPIO_DIR2, (void *)((Uint32)0x01));
    while(1)
    {
      GPIO_GetPushButton(1)   /* <- gets the pushbutton status */

      CSL_uhpiHwSetup (hUhpi, (CSL_UhpiHwSetup *)(GPIO_GetPushButton(1)));

    }
}

Can anyone help me figure this out?

  • 0
    Prodigy 190 points

    Hi all,

    I'll take advantage from this thread because I have a similar question:

    I am trying to write to GPIO-converted HD[8-10] pins from HPI module in a TMS320C6727 custom board but it seems not to work (there is no signal in the corresponding dsp pin) and I do not know why. I am using CSL 3.0 libraries (csl_C672x_03_00_09_00) and I had to create some enums within csl_uhpi.h file (CSL_UhpiGpioDat1 and CSL_UhpiGpioDir1, at the end of the code) to access to data1 and dir1 registers that manage HD[8-10].

    Another doubt I had during code programming was if (myHwSetup.gpioData.gpioDataX=CSL_UHPI_GPIO_DAT1_X) instruction really writes the data to be output in the corresponding GPIO or not.

    Attached you will find my code. Any help or code sample would be wonderful,

    Thank you very much,

    Best regards,

    Mi1980

    *********************************************

    LED.c

     

    #include "csl_uhpi.h"

    #include "csl_chip.h"

    #include "stdio.h"

     

    #define CSL_UHPI_MSB        0x0

    #define CSL_UHPI_UMB        0x0

    #define CSL_UHPI_CFG        0x0

    #define CSL_UHPI_CFG_FULL   0x8

    #define CSL_UHPI_CFG_EN     0x9

    #define UHPI_TEST_PASSED    0x0

     

    /* UHPI Handle Initialize to NULL */

    CSL_UhpiHandle           hUhpi = (CSL_UhpiHandle) NULL;

    /* CSL status */

    CSL_Status               status;

     

    Uint32                   response;

     

    CSL_UhpiHwSetup                          myHwSetup;

     

    /* forward declaration */

    void uhpi_error_exit (

        void

    );

     

    CSL_Status uhpi_test(

        void

    );

    /*

     * ============================================================================

     *   @func   main

     *

     *   @desc

     *     This is the main routine for the file.

     *

     *  @arg 

     *      NONE

     *

     *  @return

     *      NONE

     * ============================================================================

    */

     

     

    void main(void){

       while(1){

       

        status = uhpi_test();

        /* Comparing the HwStatus return value with the HwControl set value */

        if (status == CSL_SOK) {

            printf ("UHPI CSL example test passed\n");

        }

        else {

            printf ("UHPI CSL example test Failed\n");

        }

       }

     

    }

     

     

     

    /*

     * ============================================================================

     *   @func   uhpi_test

     *

     *   @desc

     *     This function will initialize the UHPI module and also write and read

     *      back the value from the UHPI register.

     *

     *  @arg 

     *      NONE

     *

     *  @return

     *      NONE

     * ============================================================================

    */

     

    CSL_Status uhpi_test(

        void

    )

    {

        CSL_UhpiObj              uhpiObj;

         CSL_sysInit();

     

        /* Initialiaze device config registers related to HPI */

        status = CSL_uhpiInit (NULL);

        if (status != CSL_SOK) {

            uhpi_error_exit ();

            return status;

        }

     

        /* Open the uhpi CSL module */

        hUhpi = CSL_uhpiOpen (&uhpiObj, CSL_UHPI, NULL, &status);

        if ((hUhpi == NULL) || (status != CSL_SOK)) {

            printf ("\nTEST FAILED\nERROR:CSL_UHPI open failed");

            uhpi_error_exit ();

            status = CSL_ESYS_BADHANDLE;

            return status;

        }

     

        /*

           Configure HPI to openhpi, no byte addressing,

           half word transfer, non mux mode, and paged memory

         */

     

        /* Configure upper 16 bits of destination address */

        /* Upper 8 bits */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPIAMSB, CSL_UHPI_MSB);

     

        /* Upper middle 8 bits */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPIAUMB, CSL_UHPI_UMB);

     

        /* Ensure that HPIENA bit is 0 */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG);

     

        /* Configure HPI */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG_FULL);

     

        /* Enable HPI */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG_EN);

     

      /* enable bits */

    /* GPIO_EN8 bank includes the HD[15:8] pin */ 

    myHwSetup.gpioEnable=CSL_UHPI_GPIO_EN8;

                  

    // HD[8] dir

    myHwSetup.gpioDir.gpioDir1=CSL_UHPI_GPIO_DIR1_8;

    // HD[8] write¿?

    myHwSetup.gpioData.gpioData1=CSL_UHPI_GPIO_DAT1_8;

     

    // HD[9] dir

     myHwSetup.gpioDir.gpioDir1=CSL_UHPI_GPIO_DIR1_9;

    // HD[9] write

    myHwSetup.gpioData.gpioData1=CSL_UHPI_GPIO_DAT1_9;

     

    // HD[10]

    myHwSetup.gpioDir.gpioDir1=CSL_UHPI_GPIO_DIR1_10;

    // HD[10] write

    myHwSetup.gpioData.gpioData1=CSL_UHPI_GPIO_DAT1_10;

     

    status = CSL_uhpiHwSetup(hUhpi, &myHwSetup);

     

        if (status != CSL_SOK) {

            uhpi_error_exit ();

                                  return status;

        }

        return status;

    }

     

    /******************************************************************************

    * @func uhpi_error_exit

    *

    * @desc Error in executing the example. As error is occurred closing the UHPI

    *       handle and returning.

    *

    * @arg 

    *   NONE

    *

    * @return

    *   NONE

    ******************************************************************************/

     

    void uhpi_error_exit (

        void

    )

    {

        status = CSL_uhpiClose (hUhpi);

        if (status != CSL_SOK) {

            status = status;

        }

            return;

    }

     

     

    Csl_uhpi.c

    .

    .

    .

    typedef enum {

                   /* This DAT bit corresponds to the /HD[0] pin */

                   CSL_UHPI_GPIO_DIR1_0    = 0x1,

                   /* controls/statis the level of the /HD[1] pin */   

                   CSL_UHPI_GPIO_DIR1_1    = 0x2,  

                   /* controls/statis the level of the /HD[2] pin */

                   CSL_UHPI_GPIO_DIR1_2    = 0x4,

                   /* controls/statis the level of the /HD[3] pin */    

                   CSL_UHPI_GPIO_DIR1_3    = 0x8,  

                   /* controls/statis the level of the /HD[4] pin */

                   CSL_UHPI_GPIO_DIR1_4    = 0x10, 

                   /* controls/statis the level of the /HD[5] pin */   

                   CSL_UHPI_GPIO_DIR1_5    = 0x20, 

                   /* controls/statis the level of the /HD[6] pin */

                   CSL_UHPI_GPIO_DIR1_6    = 0x40, 

                   /* controls/statis the level of the /HD[7] pin */    

                   CSL_UHPI_GPIO_DIR1_7    = 0x80, 

                   /* controls/statis the level of the /HD[8] pin */   

                   CSL_UHPI_GPIO_DIR1_8    = 0x100,

                   /* controls/statis the level of the /HD[9] pin */    

                   CSL_UHPI_GPIO_DIR1_9    = 0x200,

                   /* controls/statis the level of the /HD[10] pin */    

                   CSL_UHPI_GPIO_DIR1_10   = 0x400,

                   /* controls/statis the level of the /HD[11] pin */

                   CSL_UHPI_GPIO_DIR1_11   = 0x800,

                   /* controls/statis the level of the /HD[12] pin */    

                   CSL_UHPI_GPIO_DIR1_12   = 0x1000,

                   /* controls/statis the level of the /HD[13] pin */    

                   CSL_UHPI_GPIO_DIR1_13   = 0x2000,

                   /* controls/statis the level of the /HD[14] pin */    

                   CSL_UHPI_GPIO_DIR1_14   = 0x4000,

                   /* controls/statis the level of the /HD[15] pin */

                   CSL_UHPI_GPIO_DIR1_15   = 0x8000,

                   /* controls/statis the level of the /HD[16] pin */    

                   CSL_UHPI_GPIO_DIR1_16   = 0x10000,  

                   /* controls/statis the level of the /HD[17] pin */

                   CSL_UHPI_GPIO_DIR1_17   = 0x20000,

                   /* controls/statis the level of the /HD[18] pin */    

                   CSL_UHPI_GPIO_DIR1_18   = 0x40000,  

                   /* controls/statis the level of the /HD[19] pin */

                   CSL_UHPI_GPIO_DIR1_19   = 0x80000, 

                   /* controls/statis the level of the /HD[20] pin */    

                   CSL_UHPI_GPIO_DIR1_20   = 0x100000, 

                   /* controls/statis the level of the /HD[21] pin */

                   CSL_UHPI_GPIO_DIR1_21   = 0x200000, 

                   /* controls/statis the level of the /HD[22] pin */   

                   CSL_UHPI_GPIO_DIR1_22   = 0x400000, 

                   /* controls/statis the level of the /HD[23] pin */    

                   CSL_UHPI_GPIO_DIR1_23   = 0x800000,

                   /* controls/statis the level of the /HD[24] pin */    

                   CSL_UHPI_GPIO_DIR1_24   = 0x1000000,

                   /* controls/statis the level of the /HD[25] pin */    

                   CSL_UHPI_GPIO_DIR1_25   = 0x2000000,

                   /* controls/statis the level of the /HD[26] pin */

                   CSL_UHPI_GPIO_DIR1_26   = 0x4000000,

                   /* controls/statis the level of the /HD[27] pin */    

                   CSL_UHPI_GPIO_DIR1_27   = 0x8000000,

                   /* controls/statis the level of the /HD[28] pin */    

                   CSL_UHPI_GPIO_DIR1_28   = 0x10000000,

                   /* controls/statis the level of the /HD[29] pin */    

                   CSL_UHPI_GPIO_DIR1_29   = 0x20000000,

                   /* controls/statis the level of the /HD[30] pin */    

                   CSL_UHPI_GPIO_DIR1_30   = 0x40000000,

                   /* controls/statis the level of the /HD[31] pin */   

                   CSL_UHPI_GPIO_DIR1_31   = 0x80000000

    }CSL_UhpiGpioDir1;

     

     

    typedef enum {

                   /* This DAT bit corresponds to the /HD[0] pin */

                   CSL_UHPI_GPIO_DAT1_0    = 0x1,

                   /* controls/statis the level of the /HD[1] pin */   

                   CSL_UHPI_GPIO_DAT1_1    = 0x2,  

                   /* controls/statis the level of the /HD[2] pin */

                   CSL_UHPI_GPIO_DAT1_2    = 0x4,

                   /* controls/statis the level of the /HD[3] pin */    

                   CSL_UHPI_GPIO_DAT1_3    = 0x8,  

                   /* controls/statis the level of the /HD[4] pin */

                   CSL_UHPI_GPIO_DAT1_4    = 0x10, 

                   /* controls/statis the level of the /HD[5] pin */   

                   CSL_UHPI_GPIO_DAT1_5    = 0x20, 

                   /* controls/statis the level of the /HD[6] pin */

                   CSL_UHPI_GPIO_DAT1_6    = 0x40, 

                   /* controls/statis the level of the /HD[7] pin */    

                   CSL_UHPI_GPIO_DAT1_7    = 0x80, 

                   /* controls/statis the level of the /HD[8] pin */   

                   CSL_UHPI_GPIO_DAT1_8    = 0x100,

                   /* controls/statis the level of the /HD[9] pin */    

                   CSL_UHPI_GPIO_DAT1_9    = 0x200,

                   /* controls/statis the level of the /HD[10] pin */    

                   CSL_UHPI_GPIO_DAT1_10   = 0x400,

                   /* controls/statis the level of the /HD[11] pin */

                   CSL_UHPI_GPIO_DAT1_11   = 0x800,

                   /* controls/statis the level of the /HD[12] pin */    

                   CSL_UHPI_GPIO_DAT1_12   = 0x1000,

                   /* controls/statis the level of the /HD[13] pin */    

                   CSL_UHPI_GPIO_DAT1_13   = 0x2000,

                   /* controls/statis the level of the /HD[14] pin */    

                   CSL_UHPI_GPIO_DAT1_14   = 0x4000,

                   /* controls/statis the level of the /HD[15] pin */

                   CSL_UHPI_GPIO_DAT1_15   = 0x8000,

                   /* controls/statis the level of the /HD[16] pin */    

                   CSL_UHPI_GPIO_DAT1_16   = 0x10000,  

                   /* controls/statis the level of the /HD[17] pin */

                   CSL_UHPI_GPIO_DAT1_17   = 0x20000,

                   /* controls/statis the level of the /HD[18] pin */    

                   CSL_UHPI_GPIO_DAT1_18   = 0x40000,  

                   /* controls/statis the level of the /HD[19] pin */

                   CSL_UHPI_GPIO_DAT1_19   = 0x80000, 

                   /* controls/statis the level of the /HD[20] pin */    

                   CSL_UHPI_GPIO_DAT1_20   = 0x100000, 

                   /* controls/statis the level of the /HD[21] pin */

                   CSL_UHPI_GPIO_DAT1_21   = 0x200000, 

                   /* controls/statis the level of the /HD[22] pin */   

                   CSL_UHPI_GPIO_DAT1_22   = 0x400000, 

                   /* controls/statis the level of the /HD[23] pin */    

                   CSL_UHPI_GPIO_DAT1_23   = 0x800000,

                   /* controls/statis the level of the /HD[24] pin */    

                   CSL_UHPI_GPIO_DAT1_24   = 0x1000000,

                   /* controls/statis the level of the /HD[25] pin */    

                   CSL_UHPI_GPIO_DAT1_25   = 0x2000000,

                   /* controls/statis the level of the /HD[26] pin */

                   CSL_UHPI_GPIO_DAT1_26   = 0x4000000,

                   /* controls/statis the level of the /HD[27] pin */    

                   CSL_UHPI_GPIO_DAT1_27   = 0x8000000,

                   /* controls/statis the level of the /HD[28] pin */    

                   CSL_UHPI_GPIO_DAT1_28   = 0x10000000,

                   /* controls/statis the level of the /HD[29] pin */    

                   CSL_UHPI_GPIO_DAT1_29   = 0x20000000,

                   /* controls/statis the level of the /HD[30] pin */    

                   CSL_UHPI_GPIO_DAT1_30   = 0x40000000,

                   /* controls/statis the level of the /HD[31] pin */   

                   CSL_UHPI_GPIO_DAT1_31   = 0x80000000

    }CSL_UhpiGpioDat1;

    .

    .

    .

     

  • 0 in reply to mi1980
    TI__Guru*** 125430 points

    Uck -- too much code!  Please just copy paste the register values for the UHPI...

  • 0 in reply to Brad Griffis
    Prodigy 190 points

    Hi Brad,

    This is the code for register values of the HPI and to write in the HD[8] pin. For that purpose I have to create CSL_UhpiGpioDat1 and CSL_UhpiGpioDir1 enums as I detailed before.

    Thank you in advance,

     

        /* Configure upper 16 bits of destination address */

        /* Upper 8 bits */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPIAMSB, CSL_UHPI_MSB);

         /* Upper middle 8 bits */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPIAUMB, CSL_UHPI_UMB);

         /* Ensure that HPIENA bit is 0 */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG);

         /* Configure HPI */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG_FULL);

         /* Enable HPI */

        CSL_chipWriteReg (CSL_CHIP_REG_CFGHPI, CSL_UHPI_CFG_EN);

       /* enable bits */

    /* GPIO_EN8 bank includes the HD[15:8] pin */ 

    myHwSetup.gpioEnable=CSL_UHPI_GPIO_EN8;

      // HD[8] dir

    myHwSetup.gpioDir.gpioDir1=CSL_UHPI_GPIO_DIR1_8;

    // HD[8] write¿?

    myHwSetup.gpioData.gpioData1=CSL_UHPI_GPIO_DAT1_8;