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C6452/C6457 EDMA 3: can I read @32 bit, write @16bit

Massimo
Expert 6475 points

Hi,

I have to read 32bit words from a FIFO, mapped on the emif. And split these words in 2 different arrays, 16bit wide.

I know I can implement it with 2 chained tranfers, with a transfer from fifo to memory 32bit wide (A=4), and then a 16bit one to split the 32 bit words in 2x16bit arrays (A=2).

But is there a way to implement it with a single transfer and make a 32bit memory access on the emif to the fifo register with A=2?

Best regards
Massimo

  • 0
    TI__Guru* 84110 points

    Massimo,

    No guarantees, but it might be possible to take advantage of the TC Command optimization feature to do what you want.

    In the EDMA3 User's Guide, there is a section titled Command Fragmentation. It explains that with the right alignment and counts and indexes, 2D transfers may be combined into 1D transfers. The detail I am not sure about is whether the optimization requires that SRC and DST match, or if either side can be optimized independently. My 75% confident guess is that either side can be optimized independently.

    If you need to read 1 32-bit word per event, then you could try

    ACNT=2
    BCNT=2
    SRCBIDX=ACNT (2)
    DSTBIDX=distance to second buffer
    ABSYNC
    SRCCIDX=0
    DSTCIDX=ACNT (2)
    CCNT=number of half-words in buffer

    If you need to read multiple 32-bit word per event, then this would require that the FIFO address is mirrored at that many sequential addresses. In other words, that the FIFO at 0xE0000000 can also be read at 0xE0000004 / 8 / C, and so on. Then set BCNT=2*N where N=number of samples to read and N is a power of two.

    Or you could use self-chaining to read from just a single FIFO address if the mirroring is not possible.

    If you try this, please let me know if it works, or if it does not.

    Regards,
    RandyP