DRA821U: Changing System clock to 25MHz

Jack

Mastermind 9075 points

Hi TI

In order to catch packet loss of SGMII (1000BASET1), the system clock was changed from 19.2Mhz to 25Mhz.
Nothing unusual so far, but it seems like there should be a change in U-boot when crystal changes in the link below
If you need to change it to 25 MHz, please guide us.

Thanks.

Regards,

Jack

over 2 years ago

0 Erick Narvaez over 2 years ago

TI__Mastermind 36307 points

Hello Jack,

Can you please provide the link you mentioned, it seems to be missing.

Regards,

Erick

0 Jack over 2 years ago in reply to Erick Narvaez

Mastermind 9075 points

Eric.

Sorry I missed the link mentioned above.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/993992/am3359-uart2-output-baudrate-is-more-than-configured-value/3695020?tisearch=e2e-sitesearch&keymatch=uart%252525252520baudrate%25252525252019200#3695020

Here is the clock info for their system.


clock -------------------------------------- clk:292:89 clk:292:85 bus@100000:wiz@5060000_refclk-dig bus@100000:wiz@5060000_pll1-refclk bus@100000:wiz@5060000_pll0-refclk clk:292:88 clk:292:87 clk:292:86 clk:292:11 clk:288:14 clk:288:13 clk:288:12 clk:288:3 clk:287:4 clk:287:3 clk:287:2 clk:286:2 clk:283:2 clk:282:2 clk:280:2 clk:279:2 clk:278:2 clk:266:4 clk:253:9 clk:253:8 clk:253:7 clk:253:6 clk:253:5 clk:253:1 clk:253:4 clk:253:3 clk:253:2 clk:252:9 clk:252:8 clk:252:7 clk:252:6 clk:252:5 clk:252:1 clk:252:4 clk:252:3 clk:252:2 clk:201:17 clk:201:16 clk:201:15 clk:201:14 clk:201:13 clk:201:12 clk:201:11 clk:201:10 clk:201:9 clk:201:8 clk:201:7 clk:201:6 clk:201:5 clk:201:4 clk:201:3 clk:201:2 clk:201:1 clk:197:1 clk:195:1 clk:194:1 clk:193:1 clk:192:1 clk:191:1 clk:190:1 clk:189:1 clk:188:1 clk:187:1 clk:171:6 clk:171:5 clk:171:4 clk:171:3 clk:171:2 clk:171:0 clk:170:6 clk:170:5 clk:170:4 clk:170:3 clk:170:2 clk:170:0 clk:168:6 clk:168:5 clk:168:4 clk:168:3 clk:168:2 clk:168:0 clk:162:6 clk:162:5 clk:162:4 clk:162:3 clk:162:2 clk:162:0 clk:156:6 clk:156:5 clk:156:4 clk:156:3 clk:156:2 clk:156:0 clk:151:6 clk:151:5 clk:151:4 clk:151:3 clk:151:2 clk:151:0 clk:149:4 clk:149:3 clk:149:2 clk:146:2 clk:113:4 clk:113:3 clk:113:2 clk:113:1 clk:113:0 clk:105:0 clk:102:5 clk:102:0 clk:92:6 clk:92:5 clk:92:4 clk:92:3 clk:92:2 clk:92:1 clk:91:7 clk:91:6 clk:91:5 clk:91:4 clk:91:3 clk:91:0 clk:19:33 clk:19:16 clk:18:21 clk:18:18 clk:18:2 clk:18:17 clk:18:16 clk:18:15 clk:18:14 clk:18:13 clk:18:12 clk:18:11 clk:18:10 clk:18:9 clk:18:8 clk:18:7 clk:18:6 clk:18:5 clk:18:4 clk:18:3 clk:0:5 clk:0:4 clk:0:3 clk:0:2 clk:0:1 serdes-refclk bus@100000:wiz@5060000_cmn-refclk-dig-div

root@tgu:/sys/class/gpio/gpio485# cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty count count count rate accuracy phase cycle ------------------------------------------------------- 0 0 0 100000000 0 0 50000 0 0 0 100000000 0 0 50000 0 0 0 100000000 0 0 50000 0 0 0 100000000 0 0 50000 0 0 0 100000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 24000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 50000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 32550 0 0 50000 0 0 0 32550 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 32550 0 0 50000 0 0 0 32550 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 80000000 0 0 50000 0 0 0 125000000 0 0 50000 0 0 0 192000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 32550 0 0 50000 0 0 0 166666666 0 0 50000 1 1 0 166666666 0 0 50000 1 1 0 166666666 0 0 50000 1 1 0 125000000 0 0 50000 0 0 0 166666666 0 0 50000 0 0 0 0 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 192000000 0 0 50000 1 1 0 200000000 0 0 50000 1 1 0 200000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 192000000 0 0 50000 1 1 0 200000000 0 0 50000 1 1 0 200000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 320000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 333333333 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 58823529 0 0 50000 0 0 0 60000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 100000000 0 0 50000 0 0 0 0 0 0 50000

Thanks.

Regards,

Jack

0 Keerthy J over 2 years ago in reply to Jack

TI__Guru**** 162280 points

Jack,

Typically the DIP switch settings take care of the system clock configuration:

Are you seeing issues with clock frequencies?

- Keerthy

0 Young Han Kim over 2 years ago in reply to Keerthy J

Prodigy 220 points

Hi Keerthy J,

As mentioned above, we use 25MHz system clock instead of 19.2MHz to solve the packet loss problem at CPSW5G.

Actually, we have two problems in now. One is USB3.0 is not work correctly with SGMII interface. Other is baud rate of one of UART is not work correctly. So we thought that the change of system clock can be the reason of problem.

As your mention, we just changed DIP switch (bootstrap) and we didn't change any software. Just we want to check again that does it required any change of software part. If you can confirm, we can close this issue.

In fact, UART problem seems related with wkup_uart0 problem.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1225928/dra821u-changing-uart0-3-baudrate/4633442#4633442

- YoungHan Kim

+1 Keerthy J over 2 years ago in reply to Young Han Kim

TI__Guru**** 162280 points

Young Han Kim said:
As your mention, we just changed DIP switch (bootstrap) and we didn't change any software. Just we want to check again that does it required any change of software part. If you can confirm, we can close this issue.

I check internally and NOcode change should be necessary.

Thanks,
Keerthy

+1 Young Han Kim over 2 years ago in reply to Keerthy J

Prodigy 220 points

Hi Keerthy J,

Thanks for your confifmation.

Please close this issue.

Thanks

YoungHan Kim

Processors

Processors forum

DRA821U: Changing System clock to 25MHz

Hi TI

In order to catch packet loss of SGMII (1000BASET1), the system clock was changed from 19.2Mhz to 25Mhz.
Nothing unusual so far, but it seems like there should be a change in U-boot when crystal changes in the link below
If you need to change it to 25 MHz, please guide us.

Thanks.

Regards,

Jack

Processors

Processors forum

DRA821U: Changing System clock to 25MHz

Hi TI

In order to catch packet loss of SGMII (1000BASET1), the system clock was changed from 19.2Mhz to 25Mhz.Nothing unusual so far, but it seems like there should be a change in U-boot when crystal changes in the link belowIf you need to change it to 25 MHz, please guide us.

Thanks.

Regards,

Jack

In order to catch packet loss of SGMII (1000BASET1), the system clock was changed from 19.2Mhz to 25Mhz.
Nothing unusual so far, but it seems like there should be a change in U-boot when crystal changes in the link below
If you need to change it to 25 MHz, please guide us.