Part Number: PROCESSOR-SDK-OMAPL138
Other Parts Discussed in Thread: OMAPL138
Hi,
I am working on a customized OMAPL138 equipped device in which the OMAPL138 component should be initialized as an SPI SLAVE. A micro-controller, sends the binary program (binarized by "AISgen") according to the protocol introduced in document "SPRAB41F" to the OMAPL138 device in order to boot it. As started in document "SPRAB41F", the micro-controller waits between every two successive transmissions (2 Bytes) interval to left the OMAPL138 component process the received data (Specially before initializing the PLL).
However, the problem raises here where even after starting PLL0 at frequency 456MHz , and PLL1 (for DDR) at frequency 150 MHz (2x=300MHz), just at the time when the "Section Load Command" data is sent for the OMAPL138 component, There should be 10 Microsecond delay intervals between every two successive transmission to left the OMAPL138 component receive the data correctly and being successfully booted. When i decrease this 10 microsecond delay interval to some lower value, the received data by the OMAPL138 component becomes faulty and the boot process fails! The summation of these imposed consecutive delays makes the boot process of the OMAPL138 component to be a really timely process, such that it takes more than 10s to load a 1.6MB program on the OMAPL138 component.
Now, i need to know that if it is necessary to hold the delay between consecutive transmissions to be right 10 microseconds even after initializing PLL0 and PLL1? if the answer is No, then would you please help me to find the problem?
