AM62X-PET-CALC: Abnormal LPDDR4 driver waveform

Jingcheng,

for #2, can you try hand editing the DDR configuration file with the following changes.  This will enable the WDQS extension feature in the PHY for each data byte

#define DDRSS_PHY_65_DATA 0x00000104

#define DDRSS_PHY_321_DATA 0x00000104

For #1, i will have to investigate.

Regards,

James

HI James

For the #2 question's solution , can you provide more info of WDQS extension feature?

I can't find out the register info related to  DDRSS_PHY_65_DATA/DDRSS_PHY_321_DATA in spruiv7a-AM62x_TRM.

BR Jingcheng

Hi James

Do you mean this register for #2 question?

Any update for 1# question?

BR Jingcheng

Jingcheng,

#1 is still under investigation

Yes on #2, it enables the extended write DQS preamble by setting bitfield PHY_LP4_WDQS_OE_EXTEND_0 and PHY_LP4_WDQS_OE_EXTEND_1 (a register for each data byte)  

Some LPDDR4 DRAMs may require the write preamble to be active for a much longer period of time than the standard
JEDEC spec requires. The parameter phy_lp4_wdqs_oe_extend enables the feature to create this extended write preamble.

Did this change the behavior of DQS to meet spec?

Regards,

James

HI James

Please speed up the 1# issue investigation process.

For 2# issue, we has modified the register and the result seems ok from my side, still under cross check with Samsung.

BR Jingcheng

Yes, still working #1

For #2, could you provide scope shot of the difference if available

Thanks,

James

Hello James

BR Jingcheng

Great, thanks.  Still investigating #1

Regards,

James

Jingcheng, sorry for the delay here

I have checked this on our board.  Please change the following register in the configuration and test on your side

#define DDRSS_PHY_1399_DATA 0x000C3F91

Bit 7 in this register enables a different output mode for the DDR_RESET IO

Let me know results and i can make the change in the DDR Register Configuration tool in the next revision.

Regards,

James

Hello James

We modified the register according your suggestion, the abnormal drop issue has been fixed ,but the level is drop to 930mV low margin to VIH threshold = 880mV, Can you help check how to increase the RST level to 1.1V ?

Previous abnormal waveform.

BR Jingcheng

Greetings Jingcheng,

James is out temporarily, we will follow back up on this thread as soon as we can.

Sincerely,

Lucas

Hi Jingcheng,

do you have a pull down on this signal?  If it is similar to the pull down we have on the EVM (2.2K), this is probably too strong.  Try changing it to something like 10-20K.

Regards,

James

Hi James

The abnormal drop will be found under 10k/20k pull low condition， but not remarkable than preious  .

10k pull low 

20k pull low

BR Jingcheng

Jingcheng, are you sure the register fix was implemented in the 2 scope shots?  It appears that it wasn't.  You should not see any voltage drop with the register fix and the 10K or 20K pull down fix. 

Regards,

James 

Hi James

Yes, we has been modified register value .

Can you also test in your EVM board under 10K and 20K pull down condition?

BR Jingcheng

Jingcheng, i did test with the 2.2K pulldown and did not see any voltage drop like you show on the 10K pulldown scope shot.  The RESET signal was stable once it went high.  The register fix should clean up that signal, that is why i was suspecting the register was not changed.

Regards,

James