burn flash for EVMC6747 (OMAP-L137/TMS320C6747 Floating Point Starter Kit)

Take a look at the Bootloader App Note for info on the bootloader.

There is a flash writing utility included in the software downloaded from the registration page. The process is pretty straight forward, but let us know if you have any trouble getting this to work.

Thanks for pointing me to these. I tried but it did not work. Here is what I did.

1. The SW2 were all 0 at the begining
2. Built the dip switch example found in here C:\CCStudio_v3.3\boards\evmc6747_v1\dsp\tests\dip_switch
3. Used the downloaded AISgen for D800K001 to make the dip.bin, and later a dip.h from dip_switch.out, configured for EVM
4. Built the C:\C674x_dsp_1_00_00_03\dsp_spi_flash_writer\ccsv3.3\spiflash_writer_dsp.pjt 
5. loaded and ran spiflash_writer_dsp, typed in dspais and dip.bin in two dialogs as mentioned in C:\C674x_dsp_1_00_00_03\dsp_spi_flash_writer\readme.doc
6. Finished, and saw Reading verifying the file.. Files matched
7. Closed CCS, powered off the board, and set the SW2 to 0-1-0-1-0-0 (as in 7-2-1-0-3-?)
8. Powered on again.

Apperently it did not work, the LEDs were all off, no matter where the SW3 DIPs were. The same dip_switch.out worked just fine when loaded from CCS.

More questions:

1. It there a ready-to-boot image? I want to check if there is anything wrong with my board.
2. Does it matter where the SW2 switches are when I use CCS to load or run or burn flash?
3. Is there a way to burn flash without using CCS?

Thanks

File attached dip_switch.out, dip.h, dip.bin, screenshot of AISgen.

http://web.uvic.ca/~yli/ti/dip.zip

yli, it looks like you and I are at about the same stage with this new OMAP-L137 processor.  I just got the SPI flash to work today.  The problem you are having is that the simple example that you are building and flashing to the SPI does not include code for setting up the I/O pin MUX, PLL and seting up the EMIF A and B.  The GEL file takes care of all of this for you in CCS.  So all I did is copied the functions from the GEL file into my code and then it boots and runs correctly from the SPI Flash.  I have attached the C file that I used in my simple blinking LED project.  I used DSP/BIOS but you can ignore the BIOS and look at what I did in main.  I hope this fixes your problem.

/*
 *  Copyright 2008 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *
 *  @(#) DSP/BIOS_Examples 5,3,3 11-19-2008 (biosEx-j04)
 */
/*
 *  ======== clk.c =======
 *  In this example, a task goes to sleep # number of ticks and
 *  prints the time after it wakes up.
 *
 */

#include <std.h>

#include <log.h>
#include <clk.h>
#include <tsk.h>
#include <gbl.h>

#include "clkcfg.h"

#include "stdio.h"
#include <evmc6747.h>
#include <evmc6747_led.h>

#define SYS_BASE            0x01C14000
#define REVID               *(unsigned int*)(SYS_BASE + 0x000) 
#define DIEIDR0             *(unsigned int*)(SYS_BASE + 0x008)
#define DIEIDR1             *(unsigned int*)(SYS_BASE + 0x00C)
#define DIEIDR2             *(unsigned int*)(SYS_BASE + 0x010)
#define DIEIDR3             *(unsigned int*)(SYS_BASE + 0x014)
#define DEVIDR0             *(unsigned int*)(SYS_BASE + 0x018)
#define DEVIDR1             *(unsigned int*)(SYS_BASE + 0x01C)
#define BOOTCFG             *(unsigned int*)(SYS_BASE + 0x020)
#define CHIPREVIDR          *(unsigned int*)(SYS_BASE + 0x024)
#define KICK0R              *(unsigned int*)(SYS_BASE + 0x038) 
#define KICK1R              *(unsigned int*)(SYS_BASE + 0x03c) 
#define HOST0CFG            *(unsigned int*)(SYS_BASE + 0x040) 
#define HOST1CFG            *(unsigned int*)(SYS_BASE + 0x044)
#define IRAWSTAT            *(unsigned int*)(SYS_BASE + 0x0E0) 
#define IENSTAT             *(unsigned int*)(SYS_BASE + 0x0E4) 
#define IENSET              *(unsigned int*)(SYS_BASE + 0x0E8) 
#define IENCLR              *(unsigned int*)(SYS_BASE + 0x0EC) 
#define EOI                 *(unsigned int*)(SYS_BASE + 0x0F0) 
#define FLTADDRR            *(unsigned int*)(SYS_BASE + 0x0F4) 
#define FLTSTAT             *(unsigned int*)(SYS_BASE + 0x0F8) 
#define MSTPRI0             *(unsigned int*)(SYS_BASE + 0x110) 
#define MSTPRI1             *(unsigned int*)(SYS_BASE + 0x114) 
#define MSTPRI2             *(unsigned int*)(SYS_BASE + 0x118)
#define PINMUX0    *(unsigned int*)(SYS_BASE + 0x120) //PINMUX0
#define PINMUX1    *(unsigned int*)(SYS_BASE + 0x124) //PINMUX1
#define PINMUX2    *(unsigned int*)(SYS_BASE + 0x128) //PINMUX2
#define PINMUX3    *(unsigned int*)(SYS_BASE + 0x12C) //PINMUX3
#define PINMUX4    *(unsigned int*)(SYS_BASE + 0x130) //PINMUX4
#define PINMUX5    *(unsigned int*)(SYS_BASE + 0x134) //PINMUX5
#define PINMUX6    *(unsigned int*)(SYS_BASE + 0x138) //PINMUX6
#define PINMUX7    *(unsigned int*)(SYS_BASE + 0x13C) //PINMUX7
#define PINMUX8    *(unsigned int*)(SYS_BASE + 0x140) //PINMUX8
#define PINMUX9    *(unsigned int*)(SYS_BASE + 0x144) //PINMUX9
#define PINMUX10   *(unsigned int*)(SYS_BASE + 0x148) //PINMUX10
#define PINMUX11   *(unsigned int*)(SYS_BASE + 0x14C) //PINMUX11
#define PINMUX12   *(unsigned int*)(SYS_BASE + 0x150) //PINMUX12
#define PINMUX13   *(unsigned int*)(SYS_BASE + 0x154) //PINMUX13
#define PINMUX14   *(unsigned int*)(SYS_BASE + 0x158) //PINMUX14
#define PINMUX15   *(unsigned int*)(SYS_BASE + 0x15C) //PINMUX15
#define PINMUX16   *(unsigned int*)(SYS_BASE + 0x160) //PINMUX16
#define PINMUX17   *(unsigned int*)(SYS_BASE + 0x164) //PINMUX17
#define PINMUX18   *(unsigned int*)(SYS_BASE + 0x168) //PINMUX18
#define PINMUX19   *(unsigned int*)(SYS_BASE + 0x16C) //PINMUX19
#define SUSPSRC        *(unsigned int*)(SYS_BASE + 0x170)
#define CHIPSIG             *(unsigned int*)(SYS_BASE + 0x174)
#define CHIPSIG_CLR         *(unsigned int*)(SYS_BASE + 0x178)
#define CFGCHIP0            *(unsigned int*)(SYS_BASE + 0x17C)
#define CFGCHIP1            *(unsigned int*)(SYS_BASE + 0x180)
#define CFGCHIP2            *(unsigned int*)(SYS_BASE + 0x184)
#define CFGCHIP3            *(unsigned int*)(SYS_BASE + 0x188)
#define CFGCHIP4    *(unsigned int*)(SYS_BASE + 0x18C)

#define PLL0_BASE    0x01C11000          /*SYSTEM PLL BASE ADDRESS*/

#define PLL0_PID       *(unsigned int*) (PLL0_BASE + 0x00)  /*PID*/
#define PLL0_FUSERR    *(unsigned int*) (PLL0_BASE + 0xE0)  /*x*FuseFarm Error Reg*/
#define PLL0_RSTYPE     *(unsigned int*) (PLL0_BASE + 0xE4)  /*Reset Type status Reg*/
#define PLL0_PLLCTL     *(unsigned int*) (PLL0_BASE + 0x100)  /*PLL Control Register*/
#define PLL0_OCSEL      *(unsigned int*) (PLL0_BASE + 0x104) /*OBSCLK Select Register*/
#define PLL0_SECCTL     *(unsigned int*) (PLL0_BASE + 0x108) /*PLL Secondary Control Register*/
#define PLL0_PLLM       *(unsigned int*) (PLL0_BASE + 0x110)    /*PLL Multiplier*/ 
#define PLL0_PREDIV     *(unsigned int*) (PLL0_BASE + 0x114)    /*Pre divider*/ 
#define PLL0_PLLDIV1    *(unsigned int*) (PLL0_BASE + 0x118)    /*Diveder-1*/ 
#define PLL0_PLLDIV2    *(unsigned int*) (PLL0_BASE + 0x11C)    /*Diveder-2*/ 
#define PLL0_PLLDIV3    *(unsigned int*) (PLL0_BASE + 0x120)    /*Diveder-3*/ 
#define PLL0_OSCDIV1    *(unsigned int*) (PLL0_BASE + 0x124)    /*Oscilator Divider*/ 
#define PLL0_POSTDIV    *(unsigned int*) (PLL0_BASE + 0x128)    /*Post Divider*/ 
#define PLL0_BPDIV      *(unsigned int*) (PLL0_BASE + 0x12C) /*Bypass Divider*/
#define PLL0_WAKEUP     *(unsigned int*) (PLL0_BASE + 0x130) /*Wakeup Reg*/
#define PLL0_PLLCMD     *(unsigned int*) (PLL0_BASE + 0x138) /*Command Reg*/
#define PLL0_PLLSTAT    *(unsigned int*) (PLL0_BASE + 0x13C) /*Status Reg*/
#define PLL0_ALNCTL     *(unsigned int*) (PLL0_BASE + 0x140) /*Clock Align Control Reg*/
#define PLL0_DCHANGE    *(unsigned int*) (PLL0_BASE + 0x144) /*PLLDIV Ratio Chnage status*/
#define PLL0_CKEN       *(unsigned int*) (PLL0_BASE + 0x148) /*Clock Enable Reg*/
#define PLL0_CKSTAT     *(unsigned int*) (PLL0_BASE + 0x14C) /*Clock Status Reg*/
#define PLL0_SYSTAT     *(unsigned int*) (PLL0_BASE + 0x150) /*Sysclk status reg*/
#define PLL0_PLLDIV4    *(unsigned int*) (PLL0_BASE + 0x160) /*Divider 4*/
#define PLL0_PLLDIV5    *(unsigned int*) (PLL0_BASE + 0x164) /*Divider 5*/
#define PLL0_PLLDIV6    *(unsigned int*) (PLL0_BASE + 0x168) /*Divider 6*/
#define PLL0_PLLDIV7    *(unsigned int*) (PLL0_BASE + 0x16C) /*Divider 7*/
#define PLL0_PLLDIV8    *(unsigned int*) (PLL0_BASE + 0x170) /*Divider 8*/
#define PLL0_PLLDIV9    *(unsigned int*) (PLL0_BASE + 0x174) /*Divider 9*/
#define PLL0_PLLDIV10   *(unsigned int*) (PLL0_BASE + 0x178) /*Divider 10*/
#define PLL0_PLLDIV11   *(unsigned int*) (PLL0_BASE + 0x17C) /*Divider 11*/
#define PLL0_PLLDIV12   *(unsigned int*) (PLL0_BASE + 0x180) /*Divider 12*/
#define PLL0_PLLDIV13   *(unsigned int*) (PLL0_BASE + 0x184) /*Divider 13*/
#define PLL0_PLLDIV14   *(unsigned int*) (PLL0_BASE + 0x188) /*Divider 14*/
#define PLL0_PLLDIV15   *(unsigned int*) (PLL0_BASE + 0x18C) /*Divider 15*/
#define PLL0_PLLDIV16   *(unsigned int*) (PLL0_BASE + 0x190) /*Divider 16*/
#define PLLEN_MUX_SWITCH  4
#define PLL_LOCK_TIME_CNT 2400

/*PSC Module Related Registers*/             
#define PSC0_BASE       0x01C10000
#define PSC1_BASE       0x01E27000

#define PSC0_MDCTL   (PSC0_BASE+0xA00)
#define PSC0_MDSTAT  (PSC0_BASE+0x800)
#define PSC0_PTCMD   *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT  *(unsigned int*) (PSC0_BASE + 0x128)

#define PSC1_MDCTL   (PSC1_BASE+0xA00)
#define PSC1_MDSTAT  (PSC1_BASE+0x800)
#define PSC1_PTCMD   *(unsigned int*) (PSC1_BASE + 0x120)
#define PSC1_PTSTAT  *(unsigned int*) (PSC1_BASE + 0x128)

/*Enable Function for PSC0*/
void PSC0_lPSC_enable(unsigned int PD, unsigned int LPSC_num) {

  *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
  PSC0_PTCMD = 0x1<<PD;
  while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
  while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}

/*Enable Function for PSC1*/
void PSC1_lPSC_enable(unsigned int PD, unsigned int LPSC_num) {

  *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
  PSC1_PTCMD = 0x1<<PD;
  while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
  while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}

void Setup_PLL(void)
{
    int i = 0;

    /* Configure DSP at 300MHz, EMIFs at 133MHz */
    unsigned int DIV45_EN = 1;
    unsigned int CLKMODE = 0;
    unsigned int PLLM = 24;
    unsigned int POSTDIV = 1;
    unsigned int PLLDIV3 = 2;
    unsigned int PLLDIV5 = 5;
    unsigned int PLLDIV7 = 7;

 // Moved step 2c and 2d to step 0
   /*Set PLLEN=0 and PLLRST=0, Reset the PLL*/
    PLL0_PLLCTL &=  0xFFFFFFFE;  /*PLL BYPASS MODE*/
  
   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}   /*Make PLLEN_MUX_SWITCH as bootpacket*/

   /*Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
 PLL0_PLLCTL &= 0xFFFFFEFF; 
    PLL0_PLLCTL |= (CLKMODE<<8);  /* Make CLKSRC as BootPacket to pass the value*/

   /*Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR*/
    PLL0_PLLCTL &=  0xFFFFFFDF;
  
   /*PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Primus*/
    PLL0_PLLCTL &=  0xFFFFFDFF;

   /* Clear PLLRST bit to 0 -Reset the PLL */
   PLL0_PLLCTL &= 0xFFFFFFF7;  
 
   /*Disable the PLL output*/
   PLL0_PLLCTL |= 0x10;   
  
   /*PLL initialization sequence*/
  
   /*Power up the PLL- PWRDN bit set to 0 to bring the PLL out of power down bit*/
   PLL0_PLLCTL &= 0xFFFFFFFD;
  
   /*Enable the PLL from Disable Mode PLLDIS bit to 0 - This is step is not required for Primus*/
   PLL0_PLLCTL &= 0xFFFFFFEF;
  
   /*Program the required multiplier value in PLLM*/
   PLL0_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*If Necessary program the PLLDIVx*/
   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL0_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV5 = 0x8000 | PLLDIV5; /* Make PLLDIV5 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/

    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL0_PLLCMD |= 0x1;

 /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL0_PLLSTAT & 0x1==1) { }
       
   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL0_PLLCTL |= 0x8;
  
   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/
  
   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL0_PLLCTL |=  0x1;

   KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
   KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock)
   CFGCHIP3 |= 0x4;       // Enable 4.5 divider PLL
   CFGCHIP3 |= 0x1;       // Select 4.5 divider for EMIFB clock source only (not EMIFA)
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_System_Config( )                                                  *
 *      Configure PINMUX and other system module registers                  *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void Setup_System_Config(void)
{

    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock)

    PINMUX0  = 0x11111188;  // EMIFB, Check EMU0/RTCK
    PINMUX1  = 0x11111111;  // EMIFB
    PINMUX2  = 0x11111111;  // EMIFB
    PINMUX3  = 0x11111111;  // EMIFB
    PINMUX4  = 0x11111111;  // EMIFB
    PINMUX5  = 0x11111111;  // EMIFB
    PINMUX6  = 0x11111111;  // EMIFB
    PINMUX7  = 0x11111111;  // EMIFB, SPI0
    PINMUX8  = 0x21122111;  // UART2, McASP1, I2C0, I2C1
    PINMUX9  = 0x11011112;  // RMII CLK, McASP0, USB_DRVVBUS, UART2
    PINMUX10 = 0x22222221;  // RMII/ McASP0
    PINMUX11 = 0x11112222;  // McASP1, UART1, McASP0, MDIO (last 2 digits 0x22 for MDIO instead of GPIO)
    PINMUX12 = 0x11111111;  // McASP0 / McASP1
    PINMUX13 = 0x22111111;  // SD / McASP1
    PINMUX14 = 0x88222222;  // SD / EMIFA
    PINMUX15 = 0x21888888;  // SD / EMIFA
    PINMUX16 = 0x11111112;  // SD / EMIFA
    PINMUX17 = 0x00100111;  // EMIFA
    PINMUX18 = 0x11111111;  // EMIFA
    PINMUX19 = 0x00000001;  // EMIFA

     // CHIP CONFIG 2 Register: Enable USB1 clock
     CFGCHIP2  = 0x0000EB42; //USB0REF_FREQ=2 24 MHz, USB0PHY_PLLON=1 ,USB0PHYPWDN= 0   

}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Psc_All_On( )                                                     *
 *      Enable all PSC modules on ALWAYSON and DSP power dominas.           *
 *                                                                          *
 * ------------------------------------------------------------------------ */

void Setup_Psc_All_On(void)
{

    // PSC0
    PSC0_lPSC_enable(0, 0);
    PSC0_lPSC_enable(0, 1);
    PSC0_lPSC_enable(0, 2);
    PSC0_lPSC_enable(0, 3);  // EMIFA
    PSC0_lPSC_enable(0, 4);
    PSC0_lPSC_enable(0, 5);
    PSC0_lPSC_enable(0, 6);
    PSC0_lPSC_enable(0, 8);
    PSC0_lPSC_enable(0, 9);
    PSC0_lPSC_enable(0, 10);
    PSC0_lPSC_enable(0, 11);
    PSC0_lPSC_enable(0, 12);
    PSC0_lPSC_enable(0, 13);

 // PSC1
    PSC1_lPSC_enable(0, 1);
    PSC1_lPSC_enable(0, 2);
    PSC1_lPSC_enable(0, 3);
 PSC1_lPSC_enable(0, 4);
    PSC1_lPSC_enable(0, 5);
    PSC1_lPSC_enable(0, 6);  // EMIFB
    PSC1_lPSC_enable(0, 7);
    PSC1_lPSC_enable(0, 8);
    PSC1_lPSC_enable(0, 9);
    PSC1_lPSC_enable(0, 10);
    PSC1_lPSC_enable(0, 11);
    PSC1_lPSC_enable(0, 12);
    PSC1_lPSC_enable(0, 13);
    PSC1_lPSC_enable(0, 16);
    PSC1_lPSC_enable(0, 17);
    PSC1_lPSC_enable(0, 20);
    PSC1_lPSC_enable(0, 21);
    PSC1_lPSC_enable(0, 24);
    PSC1_lPSC_enable(0, 25);
    PSC1_lPSC_enable(0, 26);
    PSC1_lPSC_enable(0, 31);

}

void Setup_EMIFA(void)
{
    /* Use extended wait cycles to keep CE low during NAND access */
    AEMIF_AWCCR = 0xff;

    /* Setup CS2 - 8-bit normal async */
    AEMIF_A1CR = 0x00300608;
    AEMIF_NANDFCR &= ~1;

    /* Setup CS3 - 8-bit NAND */
    AEMIF_A2CR = 0x00300388;
    AEMIF_NANDFCR |= 2;

    /* Setup CS4 - 8-bit normal async */
    AEMIF_A3CR = 0x00a00504;  // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR &= ~4;

    /* Setup CS5 - 8-bit normal async */
    AEMIF_A4CR = 0x00a00504;  // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR &= ~8;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_EMIFB( )                                                          *
 *      Configure SDRAM.                                                    *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define EMIFB_BASE              0xB0000000
#define EMIFB_SDSTAT            *(unsigned int*)(EMIFB_BASE + 0x04)    //SDRAM Status Register 
#define EMIFB_SDCFG             *(unsigned int*)(EMIFB_BASE + 0x08)    //SDRAM Bank Config Register
#define EMIFB_SDREF             *(unsigned int*)(EMIFB_BASE + 0x0C)    //SDRAM Refresh Control Register
#define EMIFB_SDTIM1            *(unsigned int*)(EMIFB_BASE + 0x10)    //SDRAM Timing Register
#define EMIFB_SDTIM2            *(unsigned int*)(EMIFB_BASE + 0x14)    //SDRAM Timing Register

void Setup_EMIFB(void)
{
    // ISSI IS42S16160B-6BL SDRAM, 2 x 16M x 16 (32-bit data path), 133MHz
    EMIFB_SDCFG = 0         // SDRAM Bank Config Register
        |( 1 << 15)         // Unlock timing registers
        |( 2 << 9 )         // CAS latency is 2
        |( 2 << 4 )         // 4 bank SDRAM devices
        |( 1 << 0 );        // 512-word pages requiring 9 column address bits

    EMIFB_SDREF = 0         // SDRAM Refresh Control Register
        |( 0 << 31)         // Low power mode disabled
        |( 0 << 30)         // MCLK stoping disabled
        |( 0 << 23)         // Selects self refresh instead of power down
        |( 1040 <<0);       // Refresh rate = 7812.5ns / 7.5ns

    EMIFB_SDTIM1 = 0        // SDRAM Timing Register 1
        |( 25 << 25)        // (67.5ns / 7.55ns) - 1 = TRFC  @ 133MHz
        |( 2 << 22 )        // (20ns / 7.5ns) - 1 =TRP
        |( 2 << 19 )        // (20ns / 7.5ns) - 1 = TRCD
        |( 1 << 16 )        // (14ns / 7.5ns) - 1 = TWR
        |( 5 << 11 )        // (45ns / 7.5ns) - 1 = TRAS
        |( 8 <<  6 )        // (67.5ns / 7.5ns) - 1 = TRC
        |( 2 <<  3 );       // *(((4 * 14ns) + (2 * 7.5ns)) / (4 * 7.5ns)) -1. = TRRD
                            // but it says to use this formula if 8 banks but only 4 are used here.
                            // and SDCFG1 register only suports upto 4 banks.

    EMIFB_SDTIM2 = 0        // SDRAM Timing Register 2
        |( 14<< 27)         // not sure how they got this number. the datasheet says value should be
                            // "Maximum number of refresh_rate intervals from Activate to Precharge command"
                            // but has no equation. TRASMAX is 120k.
        |( 9 << 16)         // ( 70 / 7.5) - 1
        |( 5 << 0 );        // ( 45 / 7.5 ) - 1

    EMIFB_SDCFG = 0         // SDRAM Bank Config Register
     |( 1 << 16)
        |( 0 << 15)         // Unlock timing registers
        |( 2 << 9 )         // CAS latency is 2
        |( 2 << 4 )         // 4 bank SDRAM devices
        |( 1 << 0 );        // 512-word pages requiring 9 column address bits

  /*Program the EMIF3C_SDRAM Controller*/
//  EMIF3C_SDCFG  = 0x00008421;
//  EMIF3C_SDTIM1 = 0x10912A10; 
//  EMIF3C_SDTIM2 = 0x70090005;
//  EMIF3C_SDREF  = 0x410;
}

/*
 *  ======== main ========
 */
void main(void)
{
 Setup_System_Config( );         // Setup Pin Mux and other system module registers
    Setup_PLL();                    // Setup PLL0 (300MHz DSP, 133MHz EMIFs)

    Setup_Psc_All_On( );            // Setup All Power Domains

    Setup_EMIFA();                  // Async EMIF
    Setup_EMIFB();                  // Setup SDRAM

 /* Initialize BSL */
    EVMC6747_init( );
 /* Initialize the LED module */
    EVMC6747_LED_init( );
//    LOG_printf(&trace, "clk example started.\n");
}

int LEDtoggle = 1;
void myPRD(void) {

 if (LEDtoggle == 0) {
  LEDtoggle = 1;
  EVMC6747_LED_off( 1 );
 } else {
  LEDtoggle = 0;
  EVMC6747_LED_on( 1 );
 }

}

int LEDtask = 0;
Void taskFxn(void)
{
  //  Int value = ArgToInt (value_arg);
//    LgUns freq;
//    Float timeout, milliSecsPerIntr, cycles;

//    LOG_printf(&trace, "The time in task is: %d ticks", (Int)TSK_time());

    /* get frequency of platform */   
//    freq = GBL_getFrequency();

    /* get cpu cycles per ltime interrupt */
//    cycles = CLK_cpuCyclesPerLtime();
   
    /* computer milliseconds per ltime interrupt */
//    milliSecsPerIntr = cycles/(Float)freq;

    /* compute timeout */
//    timeout = value/milliSecsPerIntr;

//    LOG_printf(&trace, "task going to sleep for %d ticks... ", (Int)timeout);

//    TSK_sleep((LgUns)timeout);

//    LOG_printf(&trace, "...awake! Time is: %d ticks", (Int)TSK_time());

 while(1) {

  if (LEDtask == 0) {
   LEDtask = 1;
   EVMC6747_LED_off( 2 );
  } else {
   LEDtask = 0;
   EVMC6747_LED_on( 2 );
  }
  TSK_sleep(100);
 }  
}

Daniel Block said:

The problem you are having is that the simple example that you are building and flashing to the SPI does not include code for setting up the I/O pin MUX, PLL and seting up the EMIF A and B.  The GEL file takes care of all of this for you in CCS.  So all I did is copied the functions from the GEL file into my code and then it boots and runs correctly from the SPI Flash.

yli said:

More questions:

1. It there a ready-to-boot image? I want to check if there is anything wrong with my board.
2. Does it matter where the SW2 switches are when I use CCS to load or run or burn flash?
3. Is there a way to burn flash without using CCS?

Thanks you so much, Daniel and Tim. Now I am able to burn the flash and boot from it.

One trick I had to use it, the initialization routines, setup_pll() in particular should not be compiled with optimization flag on. Otherwise it will trap in infinite loop. Or maybe specify some variables as volatile can help as well.

I am glad to hear you were able to get this working. The optimizer can present some problems to functions that aren't designed for it. Let us know if you run into any more problems.

I found this post useful for my program as well.  By the way, you can test whether your .out file will run when it's flashed by removing the GEL file before connecting to the EVM.  Then the configuring scripts don't run so when you load and run the .out file, it's executing as if it were coming out of reset.  So for my DSP/BIOS program.  The only function I needed to add was the

Setup_Psc_All_On();

And of this, probably only the modules my program is using need to be powered-on.  I had code to setup PINMUXes so didn't need that.  My program doesn't use EMIFA pr EMIFB (i.e. SDRAM) so didn't need those.  I think DSP/BIOS configures PLL so that's not needed.  And it looks like the tool that generates the .bin file will configure the PLL if the option is checked so that shouldn't be needed regardless of DSP/BIOS setting up the PLL.  This is just a guess and I haven't checked this.

There is a new section in the "Getting Started Guide for C6747 - http://tiexpressdsp.com/index.php?title=Getting_Started_Guide_for_C6747", which also explains the process of Modifying PSP examples, generating an ais image, and Flashing the C6747 EVM. 

Flashing the C6747 EVM - http://www.tiexpressdsp.com/index.php?title=Flashing_the_C6747

Is there documentation on what startup routines need to be in place for a stand alone program?  I've observed a couple things related to the start-up GEL and my own program.

• As stated in previous posts, a program benefits from the GEL scripts that run when CCS connects to the target C6747.  For my application, I narrowed this down to the "Setup_Psc_All_On" function.  But most of these modules are on by default, so which ones MUST be called in my program to eliminate the need for the GEL script?
• When I blindly call the function "Setup_Psc_All_On" in my program (vs. the GEL script), the program will run w/o needing any GEL scripts to run.  But the CPU load graph shows it executing much slower (x5 slower) than when I run the default GEL script on target connect.  I narrowed this down to the Setup PLL function.  Can you explain what parts of this function I need to add to my program to make it run faster.  I thought DSP/BIOS sets up the PLL?  It does something because the clock is setup correctly and the periodic functions run correctly.  So what is it NOT doing that my program executes slower than when using the GEL script?

thanks,

Mike

Mike said:

Is there documentation on what startup routines need to be in place for a stand alone program?

Mike said:

As stated in previous posts, a program benefits from the GEL scripts that run when CCS connects to the target C6747.  For my application, I narrowed this down to the "Setup_Psc_All_On" function.  But most of these modules are on by default, so which ones MUST be called in my program to eliminate the need for the GEL script?

Mike said:

When I blindly call the function "Setup_Psc_All_On" in my program (vs. the GEL script), the program will run w/o needing any GEL scripts to run.  But the CPU load graph shows it executing much slower (x5 slower) than when I run the default GEL script on target connect.  I narrowed this down to the Setup PLL function.  Can you explain what parts of this function I need to add to my program to make it run faster.  I thought DSP/BIOS sets up the PLL?  It does something because the clock is setup correctly and the periodic functions run correctly.  So what is it NOT doing that my program executes slower than when using the GEL script?

Thanks Tim.  I also forgot that the AISgen program can configure the PLLs in the bootload program.   So when I created the .bin file, I clicked the proper check boxes in the GUI and it set the PLL for me!

Good point. Sorry for not mentioning that!

Here are the contents of the readme doc:

How to flash the DSP User Bootloader into SPI-Flash using the DSP Flash Utility

1. Open CCS3.3 and connect to the DSP.
2. Open project “spiflash_writer_dsp.pjt” in folder spi_flash_writer\ccsv3.3.
3. Build the flash utility project with either debug or release configuration.
4. Execute the flash utility. It should print out the following message. A stdin window will also be popped out to ask to input the type of binary to be flashed. Please type “dspais” in the window.

1. The second stdin window will be popped out to ask to input the path of the user bootloader binary file. Please supply the path of the file to be flashed. Note that the DSP user bootloader to be flashed needs to be in AIS format. For details on how to prepare for an AIS bootloader, please refer to TI application report SPRAB04.
2. The flash utility will continue printing out some messages, indicating that it is flashing the bootloader into SPI-flash. Once it runs successfully, the following message will be printed out.

1. Disconnect CCS from DSP and switch off the board. Set the SW2 switch on board as follows.

1. Power on the board again and the DSP should boot from SPI flash.

Please also see:

http://tiexpressdsp.com/index.php/Flashing_the_C6747_EVM

You should be aware that this code from the GEL file does not conform with the specs for the c6747 chip: the mask for the PSCx_MDSTAT register, in the last line of PSCx_lPSC_enable (where x= 0 or 1), should be 6 bits (0x3F) not 5 (0x1F).  Also, this fix is out-of-date, in that the latest version of AISgen (AISgen for D800K003) includes a facility for initializing the PSC and PINMUX registers during boot.

hi Daniel Block :

I have truoble to boot from spi flash based no DSP/Bios. Can you give me you boot flash project based no DSP/BIOS.

my email is:455312853@qq.com

really thanks