• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 99 subscribers
  • Views 445 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA829V: Some Questions about ECC

Hideaki Matsumoto
Genius 9050 points
Part Number: DRA829V

Hi,

We’ve received some questions about ECC from my customer. Could you answer to their questions below ?

1)  Can ECC multi 1bit Error be corrected as same as correctable ECC 1bit Error ?

 

2)  They think that “ECC_2B_ERR_MSK” is a register which indicates an error location. While this is in 128-byte data block units, the "ECC_2B_ERR_ADR" register, which indicates the error occurrence address, is described as a 64-byte alignment address (See 4.1.47 DRSS_ECC_2B_ERR_ADR_LOG_REG Register in J721E_registers3.pdf).

      Is this correct ?  Intuitively, they suspect that the "ECC_2B_ERR_ADR" address is a 128-byte alignment error, but can I interpret it as described in the manual?

3)  According to the 8.2.4.2 DDRSS Interrupts in the TRM, there are “ECC aggregators interrupts” and “MSMC2DDR bridge interrupts” as ECC error interrupt.

    Can any interrupts above be used for monitoring ECC error on SDRAM ? Are there any judging criteria which interrupt to choose ?

 

Thanks and regards,

Hideaki

  • 0
    TI__Mastermind 40686 points

    Hi Hideaki,

    Hideaki Matsumoto said:
    Can ECC multi 1bit Error be corrected as same as correctable ECC 1bit Error ?

    No, double bit errors are only detected and cannot be corrected. The hardware only supports single bit error correction and double bit error detection.

    Hideaki Matsumoto said:
    Is this correct ?  Intuitively, they suspect that the "ECC_2B_ERR_ADR" address is a 128-byte alignment error, but can I interpret it as described in the manual?

    I am not sure I understand what the question is. Are you trying to validate what is mentioned in the TRM?

    Hideaki Matsumoto said:
    Can any interrupts above be used for monitoring ECC error on SDRAM ? Are there any judging criteria which interrupt to choose ?

    The MSMC2DDR bridge interrupts are to be used to test inline ECC on the data written to or read from the SDRAM. Please refer to section 8.2.4.1.4 Inline ECC for SDRAM Data in the TRM.  The ECC aggregators interrupts pertain to control, config and VBUS.

    Thanks,

    Josiitaa

  • 0 in reply to Josiitaa RL
    TI__Genius 9050 points

    Hi Josiitaa,

    Thank you for your answers. For the 2nd question above, I added some more explanations below.

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 40686 points

    Hi Hideaki,

    I am checking internally with the design team. I will post an update soon.

    Thanks,

    Josiitaa

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 38170 points

    Hi Hideaki,

    The TRM matches the internal spec documents, and other SOCs that have different values have the same ratio (data block is 2x the address alignment).

    Does the customer have any data that suggests this is incorrect?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Genius 9050 points

    Hi Kevin,

    Thank you for your reply.

    >  The TRM matches the internal spec documents, and other SOCs that have different values have the same ratio (data block is 2x the address alignment).

    Could you please help to explain this a little more detail ?

    Do You mean like below ?

    As DDRSS_ECC_2B_ERR_ADR_LOG_REG is for address, 64-Byte aligned.

    As DDRSS_ECC_2B_ERR_MSK_LOG_REG is data, 128-Byte aligned ?

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 38170 points

    Hideaki,

    You / customer are making the statement that the TRM is incorrect because the ERR_ADR_LOG is 64 byte address aligned and the ERR_MSK_LOG is 128 bytes. 

    Why do you / customer think this is incorrect? 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Genius 9050 points

    Hi Kevin,

    The customer understood that there is no incorrect information regarding 64-Byte aligned (DDRSS_ECC_2B_ERR_ADR_LOG_REG) )and 128-Byte aligned (DDRSS_ECC_2B_ERR_MSK_LOG_REG)  in the TRM.

    They'd like to confirm about the Question (1) below.

    >    >    Can ECC multi 1bit Error be corrected as same as correctable ECC 1bit Error ?
    >    No, double bit errors are only detected and cannot be corrected. The hardware only supports single bit error correction and double bit error detection.
    a) Are "multiple 1-bit errors" recoverable unlike "ECC 2bit errors"?
    [Supplement] TRM (*1) states that "multiple 1-bit errors" are notified by an irreparable interrupt like "ECC 2bit error". But, The explanation is to the effect that it is reported as a fatal error to ensure compatibility, and it does not explicitly say that it cannot be repaired.

    (2) Is ECC error monitoring for SDRAM possible with "ECC aggregators interrupts"? (*2)
    (3) If "ECC Aggregator Interrupt" can monitor SDRAM ECC errors, it can be interpreted that both "ECC Aggregator Interrupt" and "MSMC2DDR Bridge Interrupt" can monitor SDRAM ECC errors.In this case, how should we think about the proper use of "interrupts" for both?
    Please tell them the criteria for that judgment.

    *1: "8.2.4.1.4.2 ECC Statistics" in the Technical Reference Manual
    *2: "8.2.4.2 DDRSS Interrupts" in the Technical Reference Manual
    Thanks and regards,
    Hideaki
  • +1 in reply to Hideaki Matsumoto
    TI__Mastermind 40686 points

    Hi,

    Hideaki Matsumoto said:
    Are "multiple 1-bit errors" recoverable unlike "ECC 2bit errors"?

    As mentioned in section 8.2.4.1.4.2 ECC Statistics of the TRM, the probability of receiving multiple 1-bit errors in different data words of the same SDRAM burst is very low. The chances are that there are multi-bit errors in each data word. Therefore, for reliability, pessimistic approach is taken to report these as
    a fatal error and therefore it cannot be repaired.

    Hideaki Matsumoto said:
    Is ECC error monitoring for SDRAM possible with "ECC aggregators interrupts"? (*2)

    For SDRAM integrity, the MSMC2DDR bridge interrupts are to be used to test inline ECC on the data written to or read from the SDRAM.

    Hideaki Matsumoto said:
    In this case, how should we think about the proper use of "interrupts" for both?

    Inline ECC for SDRAM is enabled by programming the bits in the DDR register and not the ECC aggregators. In this case, ECC is stored
    together with the data, and the separate ECC Aggregator Interrupts are not used.

    Thanks,

    Josiitaa