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AMIC110: DQS[x]-to-DQ[x] Skew

Hideaki Matsumoto
Expert 8420 points
Part Number: AMIC110

Hi,

My customer is asking us about DDR3 design pattern. Could you help to answer to their questions below ?

There is the following table in the datasheet.

This table describes that “DQS[x]-to-DQ[x] skew” should be MAX 25 mils”.

 

Q1)  “mils” means “mil” (1mil == 0.0254mm), correct ?

 

Q2)  If so, the difference of thees pattern line length must be less than 25mils (0.635mm), correct ?

        If so, the customer thinks that it’s tough requirement. It’s too short.

 

Q3)  Is this stripline ? or micro-stripline ?

 

Q4)  According to the AC timing characteristics, it seems that there is some margin in setup and hold. So, they don't think equal lengths are necessary.

They want to know the formula from which 25mils was derived. Could you tell them ?

Due to board size restrictions, isometric wiring is actually difficult. If this value is applied, even one interlayer via hole will deviate from this value.

 

Thanks and regards,

Hideaki

  • +1
    TI__Guru* 75090 points

    Hi Hideaki-san,

    1) that is correct

    2) Yes, the skew among all of the signals of a byte lane (DQSx and DQx, DMx) must be within 25mils

    3) This is trace length requirement for any layer

    4) i don't know if there is a specific formula,  These requirements were generated for those customers who could not perform board simulations and needed design guidelines to guarantee operation.  It is certainly possible to design a board outside of some of these requirements, but in that case i would recommend board level simulation be performed.  Note that AMIC110 does not have any hardware leveling (only software leveling via software algorithm), so this should be used especially if using multiple devices in a fly-by topology.  Will they just be using one DDR device?

    Regards,

    James