Hi All ,
I understand from the datasheet of TMS320C6678 DSP that there exists a PLL that generates the bit clock for Serdes module in Hyperlink block . This PLL takes the MCMCLKP/N clock as input and generates the bit clock. How do we configure the multipliers/dividers for this PLL. I was not able to locate any info related to the MCM Serdes PLL in any of the documents. I am interested to know whether the hyperlink can be run at lower rates i.e.lesser than 12.5 Gbps by configuring the PLL .
Any poionters will be appreciated.
-Anil