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DRA821U-Q1: Power Dissipation of CPU rail

Balkis Mahammad
Prodigy 140 points
Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821, DRA821U, LP8764-Q1, TPS6594-Q1

Hello,

We need the following details which is not available in the existing documentation of DRA821U-Q1 for power calculation of our design. Request you to provide the details.

  • Maximum power dissipation for each CPU power rail
  • Is there any integrated PMIC available from TI for the DRA821 CPU

Thanks and Regards

Balkis

  • 0
    TI__Guru 54887 points

    Balkis,

    This appnote covers the recommended power solution:

    Powering DRA821 with TPS6594-Q1 and LP8764-Q1 (Rev. A)

    Design files (schematic and PCB) are included in the EVM package:

    https://www.ti.com/tool/J7200XSOMXEVM

    Regards,

    Kyle

  • 0 in reply to kcastille
    Prodigy 140 points

    Hello,

    Thanks for reply.

    As per the EVK design design I have few queries which is listed below,

    1. As per the datasheet, VDD_MCU and VDD_MCU_WAKE1 pin typical value is 0.8V. can I connect this pin to VDD_CPU/VDD_CORE supply? 

    2. I would like to optimize the power design. Hence  can we get the power consumption of below pins

    VDD_MCU, VDD_MCU_WAKE1, VDD_CPU and VDD_CORE 

    Regards,

    Balkis

  • 0 in reply to Balkis Mahammad
    TI__Guru 54887 points

    Balkis,

    Please refer to this appnote as an alternate/lower cost implementation:

    https://www.ti.com/lit/ug/slvucd4/slvucd4.pdf?ts=1685733979714

    Regards,

    Kyle

  • 0 in reply to kcastille
    Prodigy 140 points

    Hello Kyle,

    Thanks for the appnote.

    We have referred the both mentioned userguide for calculating the power required for DRA821U chip and have listed few queries;

    Approach1
    slvuby7a -> Powering DRA821 with TPS6594-Q1 and LP8764-Q1

    Approach2
    slvucd4 -> Guide2
    Powering JacintoTM 7 J7200 DRA821 with Single TPS6594-Q1 PMIC, PDN-2A
    Query:
    1. The VDD_CPU consumption varies from 5A to 7A, what is the reason for increase in current of VDD_CPU in single PMIC approach? what is the required current?
    2. For VDD_MCU, the 0.85V is configured in slvuby7a document. but in single PMIC aproach the MCU voltage is combined with main processor power and volatge is mentioned a 0.8V. IS this different is just to optimise the regulator or holds any reason for this voltage change?
    3. VDDAR_x current requirement changes from 3.5A to 0.5mA, what is the actual requirement?
    4. What is the exact requirement for VDDA_x voltage rails? there is lot of difference in the current considered in both approach.

    Please let us know your input on this

    Regards,

    Balkis

  • 0 in reply to Balkis Mahammad
    TI__Guru 54887 points

    1. VDD_CPU peak current is ~4.5A.  In the 2nd solution, 2*3.5A bucks are used to feed that domain.

    2. Just to optimize the regulator mapping.

    3. VDDAR_* peak current is ~350 mA.  

    4. The main difference between the two topologies is that one is providing "isolated MCU and MAIN" domains, which is desirable for certain "safety" systems (this is an end user objective, not a mandate from TI).   The second solution is obviously lower cost and as such combines the MCU and MAIN domains.  And also combines some of the vdda* domains.  The vdda_* are analog domains that should be treated very carefully (max 25mV noise allowed), and at minimum have filter(s) near the SoC.  In an ideal world there would be separate LDOs feeding the vdda PLL and vdda PHY separately.  You can see the detailed implementation on the EVM schematics and layout.

    Regards,

    Kyle

  • 0 in reply to kcastille
    Prodigy 140 points

    Dear Kyle,

    Thank you for the information.

    We would like to have isolated MCU and MAIN domains in our design but cannot to have the both the PMIC due to size restriction of application board. So would lie to optimize the power in available power design. So could you please tell us what should be the approximate current requirement for MCU and MAIN domain VDDA_* rails.

    Attached the rail differences we observed in the two approaches.

    Regards

    Balkis

  • 0 in reply to Balkis Mahammad
    Prodigy 140 points

    Hello Kyle,

    Is there any input for me on above request?

    Regards,

    Balkis

  • 0 in reply to Balkis Mahammad
    TI__Guru 54887 points

    Balkis,

    In the spirit of those two implementations, I would recommend a minimum 300 mA LDO whether those domains are combined or separated.

    Regards,
    Kyle

  • 0 in reply to kcastille
    Prodigy 140 points

    Hi Kyle,

    Thanks for the response.

    In the 2 PMIC approach the VDD_CORE and SerDes(VDDA_0P8_SERDES0,VDDA_0P8_SERDES0_C and VDDA_0P8_USB) voltage is from same buck source of 5A. What is the current required for only SerDes rails? and if am using only 2 SerDes lanes for PCIe interface what is the current required for SerDes.

    Regards,

    Balkis

  • 0 in reply to Balkis Mahammad
    Prodigy 140 points

    HI Kyle,

    Any inputs on above request?

    Regards,

    Balkis