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TDA4VH-Q1: Ethernet Ports

Nuri Seko
Prodigy 160 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hello Everyone!

Hope this query finds you well!

I was looking through the datasheet of TDA4VH-Q1 ( https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf ) and in the section tittled "High speed serial interfaces:" there are 8 external ports mentioned, while on the section tittled: " Ethernet" it is mentioned that there are only 2 RGMII/RMII interfaces.

Can you help clarify what the optimal/maximal data output from the SoC to outside through the ethernet ports is? Also what the maximal data throughput per port is for the SoC? I read quite a few high speed ethernet interfaces while loking through the datasheet, but seems like they all only apply to the "switch" section of the ethernet of the SoC, not to the ethernet output of the SoC itself.

Thank you in advance!

Nuri 

  • 0
    TI__Guru 63390 points

    Hi,

    TDA4VH has two instances of CPSW2G one in MCU domain and one in Main Domain, these are supports only RGMII/RMII.

    Apart from above TDA4VH has one instance of CPSW9G (8 External Ports: Out of those only 2 Ports can be configured in 5G/10G speed and all ports supports SGMII 1G, 2.5G (XAUI) speeds).
    CPSW9G doesn't supports RGMII/RMI it supports only SGMII, XAUI,  QSGMII, XFI, USXGMII.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 160 points

    Hello Sudheer,

    Thank you for the detailed information!

    While looking through the datasheet I saw the term "QSGMII", I'm not sure I understand how that concept is related to CPSW9G, but a few questions I have  are: 

    1) The 8 external ports described above for CPSW2G are connected to only 1 internal port?

    2) The QSGMII was mentioned to be able to be assigned to 2 ports, are these two ports amongst the 8 internal ones? 

    3) What is the data throughput of CPSW9G in the QSGMII format port when 4 SGMII ports are connected to it with 1 SerDes being used for it? (only 1 QSGMII) Do you have any documents explaining how it functions?

    4) Can QSGMII support 1 x 1Gbps port + 1 x 2.5Gbps port + 1 x 5Gbps port + 1 x 10Gbps port at the same time?

    Thank you in advance,

    Nuri

  • +1 in reply to Nuri Seko
    TI__Guru 63390 points

    Hi,

    Nuri Seko said:
    While looking through the datasheet I saw the term "QSGMII", I'm not sure I understand how that concept is related to CPSW9G, but a few questions

    QSGMII is combination of 4 Ports out of those one is main lane and other 3 were sub lanes.

    Nuri Seko said:
    1) The 8 external ports described above for CPSW2G are connected to only 1 internal port?

    CPSW2G means one external port and one internal port.
    CPSW9G means 8 external ports and one internal port.
    Internal port is always 1 can be called as CPPI (communications port programming interface)

    CPSW2G supports only one external port in RGMII/RMII interface alone.

    Nuri Seko said:
    2) The QSGMII was mentioned to be able to be assigned to 2 ports, are these two ports amongst the 8 internal ones? 

    As per above QSGMII (4 lanes), we can avail 2 QSGMII ports as we have 8 Ports.

    Nuri Seko said:

    3) What is the data throughput of CPSW9G in the QSGMII format port when 4 SGMII ports are connected to it with 1 SerDes being used for it? (only 1 QSGMII) Do you have any documents explaining how it functions?

    4) Can QSGMII support 1 x 1Gbps port + 1 x 2.5Gbps port + 1 x 5Gbps port + 1 x 10Gbps port at the same time?

    It's a generic configuration QSGMII is 8/10 encoding and decoding so we configure SerDes in 5Gbps link to get 4Gbps actual data throughput over 4 lanes (each lane has 1G configuration). If you download RTOS SDK you can find QSGMII configuration by default.

    Best Regards,
    Sudheer