AM625: Watchdog timeout

Magnus Lövdahl

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG,

Hello

I have the watchdog up and running, but I have issue with the timeout.

I am running an am62 with Linux SDK 08.06.00.42.

If I start the watchdog and read out the timeout with ioctl WDIOC_GETTIMEOUT I got 60 seconds. But it takes about 150 seconds before it to reset. What could be wrong?

Also how do I change the timeout, ioctl WDIOC_SETTIMEOUT seems not to implemented in rti_wdt.c.

Is it possible to start the watchdog with a specific timeout?

Regards

Magnus

over 2 years ago

0 Nick Saulnier over 2 years ago

TI__Guru** 101250 points

Hello Magnus,

I am not aware of us providing an option to modify the watchdog timer counter value. Can you tell us a bit more about your usecase and why it needs different timeouts than the default?

Regards,

Nick

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello

Okej, I must implement changing the timeout myself.

We need to have a shorter timeout and the reason for that is safety reasons. We cannot have a timeout of 60 seconds that is too long.

What about that the octl WDIOC_GETTIMEOUT gives 60 seconds. But it takes about 150 seconds before it to reset. What could be wrong there?

/Magnus

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Hello Magnus,

what kinds of timeout would you be expecting? I might need to send your thread over to one of our folks who know more about safety than I do.

I am on vacation until Tuesday. Please ping the thread if you do not have a response by Wednesday.

Regards,

Nick

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello,

We need a timeout of about 1 or 2 second for our application.

My only issue right now is that my timeout time on my board is about 150s when it should be 60s.

I have tested with the AM62 SDK Linux BSP 08.04.01.03 and there the timeout is 60s. Do you have idea what could be wrong?

Regards

Magnus

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Hello Magnus,

It looks like there should be a way to update the watchdog timer timeout. I am checking with the developers for more information, since I cannot find any public-facing documentation about the process.

In the meantime, I am reassigning your thread to another team member more familiar with safety applications to discuss usecase.

Regards,

Nick

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello,

I have modified the rti_wdt driver and printing out some registers every second.

What I can see is that we have the same register setting but am62SDK board is counting down register (Digital Watchdog Down Counter) “wdt->base + 0xa0” faster than my custom board. About 1030 ticks vs 406 tick.

This leads me to RTI_CLK.

Where do I control/setup the RTI_CLK?

am62SDK printouts

[   41.611160] rti_wdt_get_timeleft_ms 58182 1031
[   41.615650] wdt->base + 0x0 0
[   41.618607] wdt->base + 0x4 0
[   41.621583] wdt->base + 0x90 a98559da
[   41.625256] wdt->base + 0x94 f0
[   41.628403] wdt->base + 0x98 0
[   41.631457] wdt->base + 0xa0 1d14cc
[   41.634947] wdt->base + 0xa4 a
[   41.637992] wdt->base + 0xa8 50
Time left 58
[   42.641331] rti_wdt_get_timeleft_ms 57152 1030
[   42.645807] wdt->base + 0x0 0
[   42.648794] wdt->base + 0x4 0
[   42.651779] wdt->base + 0x90 a98559da
[   42.655451] wdt->base + 0x94 f0
[   42.658581] wdt->base + 0x98 0
[   42.661634] wdt->base + 0xa0 1c90ee
[   42.665121] wdt->base + 0xa4 a
[   42.668175] wdt->base + 0xa8 50
Time left 57
[   43.671499] rti_wdt_get_timeleft_ms 56122 1030
[   43.675976] wdt->base + 0x0 0
[   43.679012] wdt->base + 0x4 0
[   43.681969] wdt->base + 0x90 a98559da
[   43.685644] wdt->base + 0x94 f0
[   43.688796] wdt->base + 0x98 0
[   43.691850] wdt->base + 0xa0 1c0d0e
[   43.695340] wdt->base + 0xa4 a
[   43.698383] wdt->base + 0xa8 50
Time left 56

My costum board printouts

[  174.656083] rti_wdt_get_timeleft_ms 59434 406
[  174.661073] wdt->base + 0x0 0
[  174.664047] wdt->base + 0x4 0
[  174.667567] wdt->base + 0x90 a98559da
[  174.671318] wdt->base + 0x94 f0
[  174.674504] wdt->base + 0x98 0
[  174.678072] wdt->base + 0xa0 1db684
[  174.681635] wdt->base + 0xa4 a
[  174.684680] wdt->base + 0xa8 50
Time left 59
[  175.688522] rti_wdt_get_timeleft_ms 59028 406
[  175.692974] wdt->base + 0x0 0
[  175.695942] wdt->base + 0x4 0
[  175.699676] wdt->base + 0x90 a98559da
[  175.703467] wdt->base + 0x94 f0
[  175.707147] wdt->base + 0x98 0
[  175.710268] wdt->base + 0xa0 1d8281
[  175.713804] wdt->base + 0xa4 a
[  175.717362] wdt->base + 0xa8 50
Time left 59
[  176.720694] rti_wdt_get_timeleft_ms 58621 407
[  176.725108] wdt->base + 0x0 0
[  176.728512] wdt->base + 0x4 0
[  176.731550] wdt->base + 0x90 a98559da
[  176.735259] wdt->base + 0x94 f0
[  176.738946] wdt->base + 0x98 0
[  176.742086] wdt->base + 0xa0 1d4e83
[  176.745687] wdt->base + 0xa4 a
[  176.749360] wdt->base + 0xa8 50
Time left 58

Regards

Magnus

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Hello Magnus,

It looks like TI just uses the standard Linux watch dog timer (WDT) interface. the API documentation is here:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/watchdog/watchdog-api.rst

Does that get things working the way you are hoping?

Regards,

Nick

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello

As I wrote in my original question the ioctl WDIOC_SETTIMEOUT seems not to be implemented in rti_wdt.c.

So you can’t change the timeout with the standard Linux watch dog timer (WDT) interface, but this is not my issue.

My issue is that I have another timeout when 60 seconds is set. I have about 150 seconds timeout. See my previous comment.

/Regards

Magnus

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Hello Magnus,

Apologies. I have grabbed your thread back for now on this side. I am following up separately with the developer about your observation that the ioctl commands seem to be missing in rti_wdt.c.

As far as the discussion of checking the clock frequencies and selecting clock masters, that is selected in the Linux devicetree node variables clocks / assigned-clocks / assigned-clock-parents

This FAQ I made for changing PRU clock might be helpful for understanding how to check clock rates & change clocking settings:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1049800/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-linux

Information that is missing from that FAQ:
Clock tree tool to visualize clocking connections is in SysConfig under
Software product: AM6X Clock Tree > Device: AM62x
AM62x clock identifiers are here: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html

I am checking to see if there are any cleaner "how to change the clocking" resources.

Regards,

Nick

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello

It looks that my RTI_CLK is correct configured

If I compare “cat /sys/kernel/debug/clk/clk_summary”, my costum vs am62 evm kit the clocks for DeviceID 125 to 130 (AM62X_DEV_RTI0 to AM62X_DEV_RTI15), all of them point at clock number 2 “
DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0”

If these clocks are correct maybe the incoming clock “DEV_RTI0_VBUSP_CLK” is incorrect, but I cannot find any info about that clock. Where is that coming from?

I have attached the printout form clk_summary both from my custom board and the eva kit.

My custom board

r

clock --------------------------------------- clk:189:6 clk:189:5 clk:189:4 clk:189:3 clk:189:2 clk:189:1 clk:188:6 clk:188:5 clk:188:4 clk:188:3 clk:188:2 clk:188:1 clk:187:0 clk:186:6 clk:186:4 clk:186:3 clk:186:2 clk:186:0 clk:182:4 clk:182:3 clk:182:0 clk:174:0 clk:173:0 clk:172:0 clk:148:0 clk:147:0 clk:146:2 clk:146:1 clk:146:0 clk:138:0 clk:137:0 clk:136:0 clk:135:0 clk:130:4 clk:130:3 clk:130:2 clk:130:0 clk:130:1 clk:128:4 clk:128:3 clk:128:2 clk:128:0 clk:128:1 clk:127:4 clk:127:3 clk:127:2 clk:127:0 clk:127:1 clk:126:4 clk:126:3 clk:126:2 clk:126:0 clk:126:1 clk:125:4 clk:125:3 clk:125:2 clk:125:0 clk:125:1 clk:117:8 clk:117:7 clk:117:6 clk:117:2 clk:117:1 clk:117:0 clk:106:2 clk:104:2 clk:102:2 clk:98:6 clk:98:5 clk:98:4 clk:98:3 clk:98:2 clk:98:1 clk:86:0 clk:81:20 30040000.pruss.coreclk-mux 30040000.pruss.iepclk-mux       0 clk:81:11 clk:81:10 clk:81:9 clk:81:8 clk:81:7 clk:81:6 clk:81:5 clk:81:4 clk:81:3 clk:81:2 clk:81:1 clk:81:0 clk:79:4 clk:79:3 clk:79:2 clk:79:1 clk:79:0 clk:78:0 clk:77:0 clk:75:9 clk:75:8 clk:75:7 clk:57:8 clk:57:6 clk:57:7 clk:57:5 clk:13:11 clk:13:3 clk:13:10 clk:13:9 clk:13:8 clk:13:7 clk:13:6 clk:13:5 clk:13:4 clk:13:0 epwm_tbclk2 epwm_tbclk1 epwm_tbclk0

oot@md5board:~# cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty count count count rate accuracy phase cycle ------------------------------------------------------ 1 1 0 200000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 1 1 0 20000000 0 0 50000 1 1 0 20000000 0 0 50000 1 1 0 200000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 1 1 0 20000000 0 0 50000 1 1 0 20000000 0 0 50000 0 0 0 500000000 0 0 50000 1 1 0 250000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 170000000 0 0 50000 0 0 0 170000000 0 0 50000 1 1 0 410714285 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 50000000 0 0 50000 0 0 0 50000000 0 0 50000 0 0 0 160000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 48000000 0 0 50000 0 0 0 1250000000 0 0 50000 0 0 0 1250000000 0 0 50000 0 0 0 1250000000 0 0 50000 0 0 0 1250000000 0 0 50000 0 0 0 32552 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 32552 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 32552 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 32552 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 32552 0 0 50000 0 0 0 12500000 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 32768 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 50000000 0 0 50000 1 1 0 50000000 0 0 50000 1 1 0 50000000 0 0 50000 0 0 0 32552 0 0 50000 1 1 0 32768 0 0 50000 1 1 0 32768 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 0 0 0 96000000 0 0 50000 1 1 0 125000000 0 0 50000 0 0 0 25000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 1 1 0 80000000 0 0 50000 1 1 0 80000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 50000 0 0 0 500000000 0 0 50000 0 0 0 400000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 333333333 0 0 50000 0 0 0 333333333 0 0 50000 0 0 0 333333333 0 0 50000 0 0 0 3125000 0 0 50000 0 0 0 8138 0 0 50000 0 0 0 8192 0 0 50000 1 1 0 25000000 0 0 50000 1 1 0 25000000 0 0 50000 1 1 0 125000000 0 0 50000 1 1 0 125000000 0 0 50000 0 0 0 160000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 1 1 0 200000000 0 0 50000 1 1 0 200000000 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 250000000 0 0 50000 1 1 0 500000000 0 0 50000 1 1 0 500000000 0 0 50000 0 0 0 400000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000 0 0 0 200000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 250000000 0 0 50000 0 0 0 0 0 0 50000 0 0 0 0 0 0 50000

am62 evm kit

root@am62xx-evm:~# cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                               y
   clock                          count    count    count        rate   accuracy phase  e
-----------------------------------------------------------------------------------------
 clk:191:2                            0        0        0    96000000          0     0  0
    clk:191:0                         0        0        0    96000000          0     0  0
 clk:191:1                            0        0        0   100000000          0     0  0
 clk:187:0                            0        0        0   500000000          0     0  0
 clk:186:6                            1        1        0   250000000          0     0  0
 clk:186:4                            0        0        0           0          0     0  0
 clk:186:3                            1        1        0   170000000          0     0  0
    clk:186:2                         1        1        0   148529411          0     0  0
 clk:186:0                            0        0        0  1190000000          0     0  0
 clk:184:8                            1        1        0   200000000          0     0  0
    clk:184:6                         1        1        0   200000000          0     0  0
 clk:184:7                            0        0        0   200000000          0     0  0
 clk:184:5                            0        0        0   250000000          0     0  0
 clk:182:4                            0        0        0   500000000          0     0  0
 clk:182:3                            0        0        0   250000000          0     0  0
 clk:182:0                            0        0        0   500000000          0     0  0
 clk:174:0                            0        0        0   250000000          0     0  0
 clk:173:0                            0        0        0   250000000          0     0  0
 clk:172:0                            0        0        0   250000000          0     0  0
 clk:162:5                            0        0        0    50000000          0     0  0
 clk:162:4                            1        1        0    25000000          0     0  0
    clk:162:3                         1        1        0    25000000          0     0  0
 clk:161:5                            0        0        0    50000000          0     0  0
 clk:161:4                            1        1        0    25000000          0     0  0
    clk:161:3                         1        1        0    25000000          0     0  0
 clk:157:166                          0        0        0    25000000          0     0  0
 clk:157:165                          0        0        0    12500000          0     0  0
 clk:157:164                          0        0        0       32768          0     0  0
 clk:157:163                          0        0        0    50000000          0     0  0
 clk:157:162                          0        0        0   192000000          0     0  0
 clk:157:161                          0        0        0   200000000          0     0  0
 clk:157:160                          0        0        0       32768          0     0  0
    clk:157:158                       0        0        0       32768          0     0  0
 clk:157:159                          0        0        0    25000000          0     0  0
 clk:148:0                            0        0        0    50000000          0     0  0
 clk:147:0                            0        0        0    50000000          0     0  0
 clk:146:2                            0        0        0   160000000          0     0  0
 clk:146:1                            0        0        0    48000000          0     0  0
    clk:146:0                         0        0        0    48000000          0     0  0
 clk:138:0                            0        0        0  1250000000          0     0  0
 clk:137:0                            0        0        0  1250000000          0     0  0
 clk:136:0                            0        0        0  1250000000          0     0  0
 clk:135:0                            0        0        0  1400000000          0     0  0
 clk:130:4                            0        0        0       32552          0     0  0
 clk:130:3                            0        0        0    12500000          0     0  0
 clk:130:2                            0        0        0       32768          0     0  0
    clk:130:0                         0        0        0       32768          0     0  0
 clk:130:1                            0        0        0    25000000          0     0  0
 clk:128:4                            0        0        0       32552          0     0  0
 clk:128:3                            0        0        0    12500000          0     0  0
 clk:128:2                            0        0        0       32768          0     0  0
    clk:128:0                         0        0        0       32768          0     0  0
 clk:128:1                            0        0        0    25000000          0     0  0
 clk:127:4                            0        0        0       32552          0     0  0
 clk:127:3                            0        0        0    12500000          0     0  0
 clk:127:2                            0        0        0       32768          0     0  0
    clk:127:0                         0        0        0       32768          0     0  0
 clk:127:1                            0        0        0    25000000          0     0  0
 clk:126:4                            0        0        0       32552          0     0  0
 clk:126:3                            0        0        0    12500000          0     0  0
 clk:126:2                            0        0        0       32768          0     0  0
    clk:126:0                         0        0        0       32768          0     0  0
 clk:126:1                            0        0        0    25000000          0     0  0
 clk:125:4                            0        0        0       32552          0     0  0
 clk:125:3                            0        0        0    12500000          0     0  0
 clk:125:2                            0        0        0       32768          0     0  0
    clk:125:0                         0        0        0       32768          0     0  0
 clk:125:1                            0        0        0    25000000          0     0  0
 clk:117:8                            0        0        0    50000000          0     0  0
 clk:117:7                            1        1        0    50000000          0     0  0
    clk:117:6                         1        1        0    50000000          0     0  0
 clk:117:2                            0        0        0       32552          0     0  0
 clk:117:1                            1        1        0       32768          0     0  0
    clk:117:0                         1        1        0       32768          0     0  0
 clk:103:2                            0        0        0    96000000          0     0  0
 clk:102:2                            0        0        0    96000000          0     0  0
 clk:81:20                            0        0        0           0          0     0  0
    30040000.pruss.coreclk-mux        0        0        0           0          0     0  0
       30040000.pruss.iepclk-mux       0        0        0           0          0     0 0
 clk:81:11                            0        0        0   500000000          0     0  0
 clk:81:10                            0        0        0   400000000          0     0  0
 clk:81:9                             0        0        0           0          0     0  0
 clk:81:8                             0        0        0           0          0     0  0
 clk:81:7                             0        0        0           0          0     0  0
 clk:81:6                             0        0        0           0          0     0  0
 clk:81:5                             0        0        0   200000000          0     0  0
 clk:81:4                             0        0        0   250000000          0     0  0
    clk:81:3                          0        0        0   250000000          0     0  0
 clk:81:2                             0        0        0   333333333          0     0  0
 clk:81:1                             0        0        0   333333333          0     0  0
    clk:81:0                          0        0        0   333333333          0     0  0
 clk:79:4                             0        0        0     3125000          0     0  0
 clk:79:3                             0        0        0        8138          0     0  0
 clk:79:2                             0        0        0        8192          0     0  0
 clk:79:1                             1        1        0    25000000          0     0  0
    clk:79:0                          1        1        0    25000000          0     0  0
 clk:78:0                             1        1        0   125000000          0     0  0
 clk:77:0                             1        1        0   125000000          0     0  0
 clk:75:9                             0        0        0   160000000          0     0  0
 clk:75:8                             1        1        0   200000000          0     0  0
    clk:75:7                          1        1        0   166666666          0     0  0
 clk:58:8                             1        1        0   200000000          0     0  0
    clk:58:6                          1        1        0   200000000          0     0  0
 clk:58:7                             0        0        0   200000000          0     0  0
 clk:58:5                             0        0        0   250000000          0     0  0
 clk:57:8                             1        1        0   200000000          0     0  0
    clk:57:6                          1        1        0   200000000          0     0  0
 clk:57:7                             0        0        0   200000000          0     0  0
 clk:57:5                             0        0        0   250000000          0     0  0
 clk:13:11                            1        1        0   500000000          0     0  0
    clk:13:3                          1        1        0   500000000          0     0  0
 clk:13:10                            0        0        0   400000000          0     0  0
 clk:13:9                             0        0        0           0          0     0  0
 clk:13:8                             0        0        0           0          0     0  0
 clk:13:7                             0        0        0           0          0     0  0
 clk:13:6                             0        0        0           0          0     0  0
 clk:13:5                             0        0        0   200000000          0     0  0
 clk:13:4                             0        0        0   250000000          0     0  0
 clk:13:0                             0        0        0   250000000          0     0  0
 epwm_tbclk2                          0        0        0           0          0     0  0
 epwm_tbclk1                          0        0        0           0          0     0  0
 epwm_tbclk0                          0        0        0           0          0     0  0
 hdmi-mstrclk                         0        0        0    12288000          0     0  0
 clk-0                                0        0        0    12288000          0     0  0

Regards

Magnus

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello,

Any info

Regards

Magnus

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Hello Magnus,

I got this information from the developers:

Ioctl is implemented by drivers/watchdog/watchdog_dev.c. eg:

                break;
        case WDIOC_SETTIMEOUT:
                if (get_user(val, p)) {
                        err = -EFAULT;
                        break;
                }
                err = watchdog_set_timeout(wdd, val);
                if (err < 0)
                        break;
                /* If the watchdog is active then we send a keepalive ping
                 * to make sure that the watchdog keep's running (and if
                 * possible that it takes the new timeout) */
                err = watchdog_ping(wdd);
                if (err < 0)
                        break;
                fallthrough;
        case WDIOC_GETTIMEOUT:

This calls ->start and -> ping callbacks of registered driver:
and drivers/watchdog/rti_wdt.c implements these callback:
static const struct watchdog_ops rti_wdt_ops = {
.owner = THIS_MODULE,
.start = rti_wdt_start,
.ping = rti_wdt_ping,
.get_timeleft = rti_wdt_get_timeleft,
};

I ran out of time today before I could finish testing trying to use the watchdog APIs on my side.

Have you tried to trace the clock path in the clock tree tool linked in the prior response? That might help us track DEV_RTI0_VBUSP_CLK

Regards,

Nick

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello,

We just received a new batch of our custom am62 boards with HS modules.

I use SDK 08.06.00.42.

Compiling SBLs and U-boot with “hs-fs”, downloading and running the watchdog. The timing works as it should.

If use the same SW with our old boards with GP modules and compile the same code with “gp”, downloads to the old boards and running watchdog. The timing is different and don’t work as it should.

I don’t know if the am625 HS CPU modules is newer with better SW or if it is the GP vs HS software that is linked together with my SBL that is the problem.

Do you have an idea about that?

The WDIOC_SETTIMEOUT is implemented in that layer(drivers/watchdog/watchdog_dev) but it use the driver layer where it is not implemented so you can’t change the timing.

Regards

Magnus

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Hello Magnus,

Hmm, interesting. I would not expect HS-FS and GP silicon to work differently.

One issue that I have seen before on SDK 8.5 is that the FIT image was the default used for boot with HS-FS, instead of the usual separate kernel image and dtb file (so people would make changes to the kernel image / dtb file, but their boards continued to boot with the FIT image, so the changes were not getting applied). However, it looks like that behavior changed on SDK 8.6 so that GP and HS-FS both default to using the separate kernel image + dtb. For more information, reference https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/08_06_00_42/exports/docs/linux/Foundational_Components_Migration_Guide.html?#linux-kernel

I am sending your thread over to a team member more familiar with GP & HS-FS differences to comment.

Additional questions:

To confirm, you are using the SBL boot found in MCU+ SDK, and then the SBL is kicking off the Linux boot? (i.e., https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_06_00_18/exports/docs/api_guide_am62x/BOOTFLOW_GUIDE.html )

Or are you using the SPL boot flow that is the default in the Linux SDK? https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html#boot-flow

Regards,

Nick

0 Magnus Lövdahl over 2 years ago in reply to Nick Saulnier

Intellectual 570 points

Hello,

I am using SPL and U-Boots from Linux SDK 08.06.00.42. Only difference for our two different boards, one with GP module and one with HS module, is that I change between "gp" and "hs-fs" in the makefile.

I am not using MCU+ SDK.

Regards

Magnis

0 Nick Saulnier over 2 years ago in reply to Magnus Lövdahl

TI__Guru** 101250 points

Ahh, thanks for the confirmation. Originally sent your thread to our SBL boot contact, re-sending to the SPL boot owner.

Regards,

Nick

0 Judith Mendez over 2 years ago in reply to Nick Saulnier

TI__Expert 8500 points

Hi Magnus,

Can you please clarify if you are now having an issue with HS-FS device or the old GP device.

Some doc on watchdog that might be helpful can be found here: software-dl.ti.com/.../Watchdog.html

~ Judith

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello,

I don’t have an issue with our new custom boards with am625 HS modules on, they work as they should. It is our old custom boards with GP module that we have issues with. With the old broads the timing is different. See previous comments.

I use SDK 08.06.00.42.

Compiling SBLs and U-boot with “hs-fs”, downloading and running the watchdog. The timing works as it should on new boards with am625 HS modules.

Regards

Magnus

0 Judith Mendez over 2 years ago in reply to Magnus Lövdahl

TI__Expert 8500 points

Hi Magnus,

Thanks for the clarification.

Please allow a couple of workdays to look into this.

~ Judith

0 Judith Mendez over 2 years ago in reply to Judith Mendez

TI__Expert 8500 points

Hi Magnus,

Have verified that if you use the same Linux Kernel, modules and DTB, clocks should be the same for GP and HS-FS device:

GP:
|   125     |     0    | DEV_RTI0_RTI_CLK                                                                                     | CLK_STATE_READY     | 24000000        |
|   125     |     1    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                                      | CLK_STATE_READY     | 24000000        |
|   125     |     2    | DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0                                                          | CLK_STATE_READY     | 32768           |
|   125     |     3    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT                                                       | CLK_STATE_READY     | 12500000        |
|   125     |     4    | DEV_RTI0_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT0_DIV_CLKOUT                                            | CLK_STATE_READY     | 32552           |
|   125     |     5    | DEV_RTI0_VBUSP_CLK                                                                                   | CLK_STATE_READY     | 125000000       |

HS-FS:
|   125     |     0    | DEV_RTI0_RTI_CLK                                                                                     | CLK_STATE_READY     | 24000000        |
|   125     |     1    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                                      | CLK_STATE_READY     | 24000000        |
|   125     |     2    | DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0                                                          | CLK_STATE_READY     | 32768           |
|   125     |     3    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT                                                       | CLK_STATE_READY     | 12500000        |
|   125     |     4    | DEV_RTI0_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT0_DIV_CLKOUT                                            | CLK_STATE_READY     | 32552           |
|   125     |     5    | DEV_RTI0_VBUSP_CLK                                                                                   | CLK_STATE_READY     | 125000000       |

~ Judith

0 Magnus Lövdahl over 2 years ago

Intellectual 570 points

Hello,

Could it be that we have early engineer sample of tour GP modules?

Regards

Magnus

0 Judith Mendez over 2 years ago in reply to Magnus Lövdahl

TI__Expert 8500 points

What samples do you have?

~ Judith

0 Magnus Lövdahl over 2 years ago in reply to Judith Mendez

Intellectual 570 points

Written on CPU

-------------------

AM6254A

TCGGAALW

29POL2S

131 G1

-------------------

Regards

Magnus

0 Judith Mendez over 2 years ago in reply to Magnus Lövdahl

TI__Expert 8500 points

Hi Magnus,

I will dig deeper into this and inform you tomorrow.

~ Judith

0 Judith Mendez over 2 years ago in reply to Judith Mendez

TI__Expert 8500 points

Hi Magnus,

Verified that

" From the hardware point of view, based on the change definition - other than the eFuse there are no known variations". Therefore there shouldn't be any difference between both devices in this case.

One recommendation given was to check if the oscillator is working.

In terms of software, we are assuming the software is exactly the same. The same tispl.bin and u-boot is used for both devices. Also, same r5 SPL, with the exception of FW. If this is true, then I believe this is not a software issue.

~ Judith

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AM625: Watchdog timeout