TDA4VH-Q1: DISABLE_PREEMPTION

Seunghyun Roh

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hello,

vx_tidl_target.c has these lines. I want to get advice for the following.

#if defined(SOC_AM62A)
/* #define DISABLE_PREEMPTION */
/* #define DISABLE_INTERRUPTS_DURING_PROCESS */
#else
/* #define DISABLE_INTERRUPTS_DURING_PROCESS */
#endif
#endif

Which case will apply for Tda4VH SoC?
What are the impact for(If you give me practical detail rather than a general statement like disable OS preemption, it will be a great help.)
- DISABLE_PREEMPTION
- DISABLE_INTERRUPTS_DURING_PROCESS

Thank you very much and great day.

Best regards,

over 2 years ago

0 Nikhil Dasan over 2 years ago

TI__Guru* 84966 points

Hi,

Seunghyun Roh said:
Which case will apply for Tda4VH SoC?

The #else part is applicable for TDA4VH.

Lemme confirm with an internal expert on why this implementation came into place.

Regards,

Nikhil

0 Anshu Jain over 2 years ago in reply to Nikhil Dasan

TI__Guru 56820 points

Hi,
Preemption is a feature which allows to preempting a deep learning model running in TIDL from a higher priority model. By default this is enabled, thats why those macro's are commented out. In terms of impact when pre-emption is enabled tidl will request some extra memory in DDR to allow context store restore.

Regards,

Anshu

0 Seunghyun Roh over 2 years ago in reply to Anshu Jain

Expert 1760 points

Hello Anshu,

How to configure the priority of models?

Best regards,

Processors

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TDA4VH-Q1: DISABLE_PREEMPTION