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TMS320C6678: EDMA3 LLD code

Part Number: TMS320C6678

Hi,

pdk_c667x_2_0_16\packages\ti\csl\example\edma\edma_test.c

Could you please briefly explain the following code in edma_test, I don't understand the configuration of .srcDstBidx, myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1). In the case of A-synchronized transfer, why not myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(Acnt, Acnt)?

  • Nancy,

    Let me look at it and get back.

    Regards

    Shankari G

  • Nancy,

    Please refer this document : https://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

    It has all the explanation on EDMA configurations.

    Please go through the code and co-relate with the doc.

    Particularly, page no: 35 

    Regards

    Shankari G

  • Hi,

    I have refer this document already. I just don't know why CSL_EDMA3_BIDX_MAKE(1,1).

  • Ok, Let me check and get back.

  • Could you please briefly explain the following code in edma_test, I don't understand the configuration of .srcDstBidx, myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1). In the case of A-synchronized transfer, why not myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(Acnt, Acnt)?

    There seems to be a separate macro for A-count and B-count entry as below. 

    "CSL_EDMA3_BIDX_MAKE" is for B index entry.

    For example, CSL_EDMA3_BIDX_MAKE(1,1) will result in 65537----> B index entry

    ( Just try expanding the macro of  " CSL_FMKR(31, 16, (Uint32)(dst)) |CSL_FMKR(15, 0 , (Uint32)(src))" with msb, lsb and src,dst values.

    -----

    Here, CSL_EDMA3_BIDX_MAKE(1,1src = 1 and dst = 1.

     

    CSL_FMKR(31, 16, (Uint32)(dst)) will give you " 1 "   

    #define CSL_FMKR(msb, lsb, val) \
    ((val & ((1 << (15 - 0 + 1)) - (1))) << (0)) 

    and

    CSL_FMKR(15, 0 , (Uint32)(src) will give you "65536"

    Finally, when 1 ( Bitwise OR operation ) with 65536 will give you 65537.

    65537---> Divide by two will yield you the unsigned integers  ranging between  -32 768 and 32 767 "

    " Valid values for DSTBIDX are between -32 768 and 32 767." Page no: 33 ---> https://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

    ----

    In edma_test.c, line no: 280, in the parameter setup, please find this line of code : "myParamSetup.aCntbCnt   = CSL_EDMA3_CNT_MAKE(256,1);  " --- > This is meant for setting up the A-count and B-count entry.

    ---

    /** Used for creating the B index entry in the parameter ram */
    #define CSL_EDMA3_BIDX_MAKE(src,dst) \
    (Uint32)(\
    CSL_FMKR(31, 16, (Uint32)(dst)) \
    |CSL_FMKR(15, 0 , (Uint32)(src))\
    )

    /** Used for creating the A,B Count entry in the parameter ram */
    #define CSL_EDMA3_CNT_MAKE(aCnt,bCnt) \
    (Uint32)(\
    CSL_FMKR(15, 0, (aCnt)) \
    |CSL_FMKR(31, 16, (bCnt)) \
    )

    ---

    I hope it helps.

    That's how B index entry is expanded and derived to 65537, to range between -32 768 and 32 767 "

    Regards

    Shankari G