AM62X-PET-CALC: How to modify the MCU_I2C0_SCL driver strength to meet PMIC65219 I2C timing spec

Hi,

Thanks for your query.

Which OS are you running on board RTOS / Linux ?

Best Regards

Ashwani

HI Ashwani

Linux.

BR Jingcheng

Hello Jingcheng,

I am not aware of Linux driver functionality to adjust signal pulse length. I am sending you over to a member of our HW team to discuss.

Regards,

Nick

Hello Jingcheng,

I assume this is a custom board.

The MCU_I2C0 is a open drain type buffer. Could you confirm the I2C pullup values that you are using. Whare are the pullups placed.

Can you try reducing the value and run some tests.

Regards,

Sreenivasa

Hello Jingcheng,

Are you connecting the I2C pulls to 3.3V. Please note that there are slew rate limits specified in the datasheet. You may need to add an RC filter. 

Regards,

Sreenivasa

Hello Jingcheng,

I have not heard from you and will need the interface waveforms to support further.

Regards,

Sreenivasa

Hello Sreenivasa

Which EVM Project do your referenced?

How R598 and C492 impact the I2C low time?

BR Jingcheng

Hello Jingcheng,

Thank you.

Jingcheng ye said:

How R598 and C492 impact the I2C low time?

This is not for I2C timing improvement but a note for you to be aware that the I2C has a slew rate limit calling for an RC circuit when pulled up to 3.3V.

Regards,

Sreenivasa

Hello Sreenivasa

So from your view , recommend to add a C492 in the I2C path to increase the SCL_L  time to meet the min low time limitation.

Is that correct?

BR Jingcheng

Hello Jingcheng,

Thank you.

Please refer to my initial message

I assume this is a custom board.

The MCU_I2C0 is a open drain type buffer. Could you confirm the I2C pullup values that you are using. Where are the pullups placed.

Can you try reducing the value and run some tests.

Did you have a chance to review and verify.

Regards,

Sreenivasa

Hello Sreenivasa

Could you confirm the I2C pullup values that you are using. Where are the pullups placed.

Jingcheng: 4k7 Pull up resistor is used, place nearby the I2C load side(PMIC).

Can you try reducing the value and run some tests.

Jingcheng: Current low time is shorter than spec listed 1.3us, we want incread the low time, why try to decreas the pull up resistor which may lead to decrease the rise time of SCL.

BR Jingcheng

Hello Jingcheng,

Thank you.

We will need the interface waveforms to support further.

Jingcheng: Current low time is shorter than spec listed 1.3us, we want incread the low time, why try to decreas the pull up resistor which may lead to decrease the rise time of SCL.

I can comment after looking at the waveform and would want you to try different pull values if possible.

Regards,

Sreenivasa

Hi Sreenivasa

BR Jingcheng

Hello Jingcheng,

Thank you for the waveform. I am checking internally.

In the meantime, could you please try adding the below RC,. based on the waveform i guess the i2C is pulled to 3.3V.

Regards,

Sreenivasa

Hello Jingcheng,

Please refer additional inputs i received:

We need to confirm the I2C module is configured properly for the operating frequency of its functional clock.

 I have seen similar things happen when a customer tells their software to configure all of the internal clocks and peripherals for a 24MHz reference clock when they actually connect a 25MHz crystal.  I’m not saying that is what is happening in this case, but something like this is a possibility.

Regards,

Sreenivasa

Hello Sreenivasa

No such configuration error in current test sample version.

BR Jingcheng

Hello Jingcheng,

Thank you.

Did you have a chance to make some measurements with the RC?

Regards,

Sreenivasa