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AM625: Read back DDR clock running frequency

Tony Tang
Mastermind 30657 points

Part Number: AM625

How to read the DDR clock running?

from the tisci user guide, 

root@am62xx-evm:/home# k3conf dump clock | grep DDR
| 157 | 24 | DEV_BOARD0_DDR0_CK0_IN | CLK_STATE_READY | 250000000 |
| 157 | 25 | DEV_BOARD0_DDR0_CK0_N_IN | CLK_STATE_READY | 0 |
| 157 | 27 | DEV_BOARD0_DDR0_CK0_OUT | CLK_STATE_READY | 0 |
| 170 | 0 | DEV_DDR16SS0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 400000000 |
| 170 | 1 | DEV_DDR16SS0_DDRSS_TCK | CLK_STATE_READY | 0 |
| 170 | 2 | DEV_DDR16SS0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
root@am62xx-evm:/home#


root@am62xx-evm:/home# k3conf dump clock 170
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-88-g982f5c2 built Fri Feb 24 05:07:09 UTC 2023) |
| SoC | AM62X SR1.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') |
|--------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|-------------------------------------------------------------------------------------------|
| 170 | 0 | DEV_DDR16SS0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 400000000 |
| 170 | 1 | DEV_DDR16SS0_DDRSS_TCK | CLK_STATE_READY | 0 |
| 170 | 2 | DEV_DDR16SS0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
|-------------------------------------------------------------------------------------------|

none of upper showing DDR running clock frequency.

  • 0
    TI__Guru* 95641 points

    Tony, clock 170 shows the setting of the PLL that drives the DDRSS.  This PLL will be 1/2 the memory clock frequency (or 1/4 of the data rate)

    So your log is showing DDR PLL = 400MHz, which means the DDR memory clock is 800MHz (1600MTs)

    Regards,

    James