CPPI details for USB on the C674x

Hi,

1. The DMA configuration and operation is agnostic of the mode the USB Controller is assuming. So, the programming is the same. You only need to pay attention to the data direction flow only. Transmit Data Buffer will be defined by Host Packet and optional Host Buffer Descriptors while Receive Data Buffer will be defined by Host Buffer Descriptors only. Yes you are correct, the fields of each words are missing. Will capture the main field description within this reply and the User's Guide will be updated soon with the required information. Thank you for pointing this out.

Both HPD is the superset of HBD. For the defined fields the meanings of the bit fields are the same for most parts. for HBD Words 0, 1, and half of Word 2 are reserved.

HPD: Word 0 [31:27]=Host Pkt Type = 0x10 which is HPD, HPDWord0[26:22]=Number of 32-bit words in the protocol specifc region (almost all application this is program with ZERO), HPD:Word0[21:0]=Packet Length (do not confuse the term packet here with a USB Packet)=The total data size to be transmitted.

HPD: Word 1[31:27]=Source Port Num=Endpoint #, HPD:Word1[26:21]=Source Channel Num=Always ZERO, HPD:Word1[20:16]=Source Sub Channel Num=Always ZERO, HPD:Word1[15:0]=Destination Tag=Always ZERO.

HPD/HBD: Word2[31]=Packet Error=Meaningful for HBD only. Port sets this bit if error occured during reception and is reserved for both HPD/HBD. HPD/HBD:Word2[30:26]=Packet Type=USB=0x5 (for HBD, Ports will populate this feld with 0x5 so it is reserved), Word2[25:15]=Reserved, HBD/HPD: Word2[14]=Descriptor Location is On/Off Chip = 1/0 respectively, HBD/HPDWord2[13:12]=Return Queue Manager=Always Zero, HBD/HPD:Word2[11:0]=Packet Return Queue=Completion Queue.

HBD/HPD:Word3[31:22]=Reserved; HBD/HPD:Word3[21:0]=Data Buffer Length for this Descriptor.

HBD/HPD:Word4[31:0]=Pointer to the Data Buffer defined by this Descriptor.

HBD/HPD:Word5[31:0]=Pointer to the NEXT HBD.

HBD/HPD:Word6[31:22]=Reserved; Word621:0]=Original Data Buffer Length for this Descriptor. Should be >= Word3[21:0]

HBD/HPD:Word7[31:0]=Pointer to the Orignal Data Buffer defined by this Descriptor.

2.  I did see the description of the registers and it seems to be confusing and require update. Since the scheduler handles 256 entries and 4 entries are allowed to be captured per a single 32 bit words, there exist 64 Words with WORD 0 handling the first 4 entries (entries 1, 2, and 3) and WORD63 handles the last 4 of the 256 entries (entries 253, 254, 255, and 256). With this description, Section 4.75 should have been documented as: CDMA Scheduler Table Word n Registers (ENTRY[0]- ENTRY[3]). The Channel # is the Endpoint Number. This will be corrected on the next release.

Having said that, there is a good description of the scheduler but would like to simplify what it is supposed to do. The scheduler handles the rate at which an endpoint is serviced, if the endpoint is scheduled for service by a user. The scheduler handles priority in a bit different matter, that is, by configuring the entries that the scheduler is designed to use. The size and content of this entry is user programmable. The user has the capability of implementing priority by the number of entries you assign. Note that the scheduler services the endpoints in a round robin fashion and the way you control priority is by the values you are programming the entries. As an example assume you would like to enable three endpoints on your system: EP1-Tx, EP2-Rx, and EP2-Tx. If you desire to assign equal priorities then the most efficient way to do this will be to inform the scheduler that you would have only 3 entries by programming DMA_SCHED_CTRL.LAST_ENTRY with 2 (which 3-1). This would instruct the scheduler to work with the first 3 entries only. Only the first word, WORD0, will be required to be used. ENTRY0_CHANNEL=1, ENTRY0_RXTX=0, ENTRY1_CHANNEL=2, ENTRY1_RXTX=1, and ENTRY2_CHANNEL=2, ENTRY2_RXTX=0.

For the same defined endpoints (EP1-Tx, EP2-Rx, and EP2-Tx) suppose you want to handle EP1-Tx to be handled 4 times as much as the others. One way to achieve this is to program DMA_SCHED_CTRL.LAST_ENTRY with 5 (which 6-1) and allocate the first 4 entries to EP1-Tx operation and the two entries of WORD1 for EP2-Rx, and EP2-Tx. This means that WORD0 could be programmed as follows (ENTRY3_CHANNEL=1, ENTRY3_RXTX=0 : ENTRY2_CHANNEL=1, ENTRY2_RXTX=0  : ENTRY1_CHANNEL=1, ENTRY1_RXTX=0 : ENTRY0_CHANNEL=1, ENTRY0_RXTX=0) while WORD1 (ENTRY1_CHANNEL=2, ENTRY1_RXTX=0   :   ENTRY0_CHANNEL=2, ENTRY0_RXTX=1).

3. Please refer to the updated User's Guide that will be released shortly and more information on this will be included there.

4. No. The 256 bytes is just an example. See reply for Question 1 for the max data size.

5. This is upto the application. Most of the time, you the application might require only a single queue. However, for ISO type of transfers you might two queues might be necessary.

6. The CPPI DMA is used by multiple peripherals (EMAC, ATM, etc) and this is DMA specific and you can ignore this comment.

7. Region 1 size is indirectly supplied since total size allowd (64K) - region 0 size.

8. You can access EP Registers directly from the non-indexed region or indirectly from Indexed region. If want to ensure no contention arises, you might want to use the non-indexed region at all time. However, few registers require access via Indexing.

Most of the concerns you have pointed here will be addressed on the next release. Thank you.

Best regards, Zegeye