pad configuration for SPI

Mohamed Osama

Hi all,

I noticed in the EVM8148 gel files that the pad configuration registers PINCNTL81, PINCNTL82, PINCNTL83 and PINCNTL84 for SPI0 is set to 0x00060001

I know that the 01 for the first byte is the function select but what is the 06 for the third byte?

over 14 years ago

0 Steve Clynes over 14 years ago

TI__Mastermind 43875 points

Bits 16 and 17 control the internal pull up/down resistors.

Bit 16 = 1 to disable the pull up/down
Bit 17 = 0 for pull down when enabled, = 1 for pull up when enabled

BR,

Steve

0 Mohamed Osama over 14 years ago in reply to Steve Clynes

Intellectual 300 points

so why 06 in third byte? 6 means 0110.

So bit 16 is 0, bit 17 is 1 and bit 18 is set to 1 what is bit18 function?

0 Steve Clynes over 14 years ago in reply to Mohamed Osama

TI__Mastermind 43875 points

OK, bit 18 should be 1 for an input since it enables the receiver.

Some pin control registers may also have bit 19 set, which in some cases controls the output slew rate.

Bits 18 & 19 should not be changed from their default settings.

BR,

Steve

0 Mohamed Osama over 14 years ago in reply to Steve Clynes

Intellectual 300 points

So for the SPI for example pin D1 could be IN or OUT and PIN D0 also.

In this case, the IN Pin should have Bit 18 set to 1?

0 Steve Clynes over 14 years ago in reply to Mohamed Osama

TI__Mastermind 43875 points

Yes, leave this as a 1.

To be honest I am not really sure why there is a control bit to enable the receiver since even when the pin is an output it is OK to leave the receiver turned on.

I think this may be a power saving feature, but I am not 100% sure.

BR,

Steve

0 Mohamed Osama over 14 years ago in reply to Steve Clynes

Intellectual 300 points

Thank you very much Steve for the answer

Could you help me configure the McSpi as slave device?

0 Steve Clynes over 14 years ago in reply to Mohamed Osama

TI__Mastermind 43875 points

Unfortunately I don't know too much about that.

I would suggest starting a new thread for this new question.

BR,

Steve

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pad configuration for SPI