There are so many questions about 'how to capture interlaced video frames from VPFE". This thread is created to just address that.
If you wan to capture D1 interlaced video from VPFE, there is no need to connect previewer and reszier in chained mode with CCDC.
Simple way will be to capture from CCDC. You need to change ISR routines though.
For example, If you are using arago source(http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/r37),
you can change vpfe_isr() and vpfe_vdint1_isr() to capture interlaced video frames.
In addition to above changes, you need to change programming of CCDC's SDOFST register in CCDC driver module [ Refer to section 6.1.15 of VPFE user guide].
some related questions
What ISR changes needed?
Currently ISR's are designed to capture progressive frames by programming same buffer address in HW when it captures ODD field and EVEN field. That is the reason "field id" comes into picture in ISR.
You have to remove that optimization and program different buffers addresses in HW for every new field capture.
Where is the magic, in chained mode, that makes the resizer skip every other line?
Regarding resizer loosing one field, I believe HW is using certain algorithm to de-interlace using one of the field's.
Does SDOFST(CCDC) register change behavior in chained mode, or only in one shot when we pull from SDRAM?
SDOFST applies only when data is written to SDRAM.