FPGA RTL Code for TMS320C6678 Eval Module

The source for the FPGA code contains some proprietary information and is currently not available.  If you have specific information on the contents of the FPGA please post them here and we will provide the details.

The customer I'm working with had this to say:

"the FPGA controls a fairly elaborate power-on sequence of enabling power supplies, clocks, etc, and to have access to the code for that state machine would be very useful"

The source code would be ideal but if not, maybe a graphical state machine of what it's doing?

The FPGA is pretty extensively documented in the technical reference manual for the EVM but I will see if I can get the designer to release the sections associated with the power on sequencing.

The EVM module is functional but the RTL code would be good for developing a new design.  The plan is to use the same Spartan 3 and hopefully the same RTL code.

Hi Tom,

Has the portion of FPGA code released in source code form? I see just binaries .bit file available from link below -

http://www.advantech.com/Support/TI-EVM/6678le_download.aspx

Thanks,

Prateek

Thanks Mike for sharing FPGA code.

The customer looked at the FPGA RTL code files that Advantech made available but could not find the information they are looking for. It is not in the EVM Technical Reference Manual either. Here is what they would like to know -

a)  what commands the FPGA sends to the UCD9222 via the PMBus_CNTL pin during power up, and under what conditions.

b) any other interaction over the other PMBus pins as part of the power-on sequence

Section 5.3 of Technical Reference Manual does not cover all the details as E2E forum post http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/131297/471863.aspx#471863 suggests that another pin PMBUS_CNTL pin need to be part of Power on Sequence that was not clear from TRM.

Is it possible to get above information?

Thanks,

Prateek

Mike,

Thanks for posting the FPGA RTL.  Yours is the file bundle that we approved for release by Advantech a few weeks back.  It should have been on their web site by now.  I wanted it to be released by that method so that the release could be controlled.

Tom

Hi Tom,

I have seen that the rtl is on the advantech website. What would be really handy is the constraints file, its hard to see from the RTL what's going on as there's definite picture of what internaly is connected externally. There are lots of pins on the FPGA which don't seem to be driven internally. Don't suppose you've seen the constraints file around?

Regards

Hef

Hef,

As stated earlier in this thread, there is no significant logic in the FPGA for customers to reuse. The FPGA is not needed to implement a Shannon solution.  It is a convenient way to integrate the EVM into a small form factor.  It basically contains 3 logic blocks: a simple power supply sequencer, programming for the clock generators over an SPI interface and reset/bootmode control.  A simple power supply sequencer like the UCD9080 can be implemented for this functionality for the entire board.  The one in the FPGa has a time-base of 5ms.  Similarly, a system controller or uC can handle the clock programming for the entire board or these devices can be pre-programmed as part of the manufacturing process.  This SPI port can run as slow as the FPGA wants.  The bootmode control can be programmed with resistors in the customer design.  There is nothing speed critical in the design.  We are not releasing a full design environment because we are not supporting customer modification of the FPGA on the EVM.  This is a support decision.  It does not limit re-use of the RTL.  The RTL posted will compile.

Tom

I'm a colleague of Hef's.  Can I ask you a question:  how long do you think this "simple power supply sequencer", clock programming, etc. would take to develop and get working?  Does TI have a handy reference design for a C6678 board not using an FPGA? 

We have at length decided we do need an FPGA on our board, at least initially.  Although we are sure your approach would work eventually, we do not have confidence we can get it to work on our tight product timescale.  An FPGA where we have a reference design seems much lower risk on that front.  It may all seem like trivial off-the-shelf glue to you, being familiar with the chip, but it looks like a whole pile of work and risk to us.

Gordon,

The RTL for this is on the EVM web site.  As an alternative, TI has a line of single-chip sequencers such as the UCD9090.  The EVM schematic and the EVM Tech Ref both have diagrams showing the sequencing solution.  The Tech Ref also has a detailed sequence description showing it is a simple linear state machine.  This should be a straight-forward and low-risk implementation in FPGA or with a chip sequencer.

Tom