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TDA4VH-Q1: U-boot start optimization

Matthew
Intellectual 300 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

hello，

I am using TDA4VH EVM board，and i‘m using sdk8.5.

My current task is to shorten the start time of the TDA4VH board Bootloader.

When C71 is not started，the time is

Then I try to analyze the source code，I found that when running tiboot3.bin firmware，there was total of five files will be loaded，They are：

1、bl31.bin       //atf

2、bl32.bin       //optee

3、ipc_echo_testb_mcu1_0_release_strip.xer5f      //in board-support/prebuilt-images/

4、u-boot-spl-nodtb.bin   //in board-support/u-boot_build/a72/spl/

5、dt-spl.dtb    // in board-support/u-boot_build/a72/dts/

when running tispl.bin firmware，there was total of two files will be loaded，They are：

1、u-boot-nodtb.bin   //in board-support/u-boot_build/a72/spl/

2、dt.dtb    // in board-support/u-boot_build/a72/dts/

I added their printing before loading their memcpy function before and after，

The strange thing is that the 5 files of tiboot3.bin spent a short time, but the two files in memcpy tispl.bin took a long time, you can see from the picture below

I want to know why the memcpy process load u-boot-nodtb.bin will spend 300ms？this time looks too long.

In addition, I also want to ask, what other methods can shorten the operation of Uboot execution time?

thank！

  • +1
    TI__Guru**** 162740 points

    Hi,

    Matthew said:
    The strange thing is that the 5 files of tiboot3.bin spent a short time, but the two files in memcpy tispl.bin took a long time, you can see from the picture below

    The size of the U-Boot is definitely more but yes I agree that its high. Can you try the below change to enable caches in A72 SPL which loads the U-Boot binary.

    diff --git a/common/spl/spl.c b/common/spl/spl.c
index 63c48fbf33df..67882bb19470 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -602,6 +602,12 @@  void board_init_r(gd_t *dummy1, ulong dummy2)
 
 	spl_set_bd();
 
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
+	(defined(CONFIG_CPU_V7A) || defined(CONFIG_ARM64) ||    \
+	 defined(CONFIG_CPU_V7R))
+	enable_caches();
+#endif
+
 #if defined(CONFIG_SYS_SPL_MALLOC_START)
 	mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
 			CONFIG_SYS_SPL_MALLOC_SIZE);


    Best Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 300 points

    HI,

            According to your suggestion, it takes effect!

    I want to know why cache can reduce MEMCPY time?

    Why not use cache by default?

    Will other problems bring?

    thanks！

  • 0 in reply to Matthew
    TI__Guru**** 162740 points
    Matthew said:

            According to your suggestion, it takes effect!

    Okay that is good to hear.

    Matthew said:

    I want to know why cache can reduce MEMCPY time?

    Why not use cache by default?

    Will other problems bring?

    Enabling data cache will surely improve the memcpy performance as the caching will enable faster access to data from CPU.

    I am checking if this can be made default but for now you can use this patch and that should not cause any side effects as it is done for A72 SPL phase.

    Closing this ticket.

    - Keerthy