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TDA4VH-Q1: EST function cannot work well when TDA4VH board runs in vxworks

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH, DRA829, TDA4VM

Hi  TI experts, 

I’m enabling the Enhanced Scheduled Traffic (EST-P802.1Qbv) function for the board TDA4VH which is running in the VxWorks operate system.

I did the coding by referring to chip manual (SPRUJ43_J784S4_TDA4AP_VP_AH_VH_TRM_vB  and J721E_DRA829_TDA4VM_AM752x_SR1.0_NDA_TRM_vlnitial) and

SDK code(ti-processor-sdk-linux-j784s4-evm-08_05_00_08). By the way, for EST function, the description of chip manual j784s4 and j721e is same.

After coding, I start to test EST function for tda4vh board. Unfortunately, EST function cannot work well.

Test Environment:  TDA4VH<-------->nxpls1028, tda4vh board directly connects to nxp ls1028 board which supports EST function.

Test introduction: We have written a set of applications for testing EST functionality.

This test procedure includes that  analyse GCL configuration and set it to driver, send traffic classes to driver, receive traffic classes from driver.

The driver sets GCL to hardware and enables ESTF, then EST works.

Here is an example for GCL configure:

{

    "schedule": {

        "cycle_time": 5000000,

        "start_sec": 0,

        "start_nsec": 0

    },

    "gate_control_list": [

        {

            "tclass_mask": 1,

            "time": 125000

        },

        {

            "tclass_mask": 64,

            "time": 125000

        },

        {

            "tclass_mask": 1,

            "time": 250000

        }

    ],

    "stream_objects": [

        {

            "stream": {

                "name": "flow1",

                "dst_mac": "00:04:9f:05:f7:21",

                "vid": 3001,

                "pcp": 6,

                "tclass": 6

            }

        }

    ]

}

From this GCL configure, the cycle Time is 500us, each cycle splits into three gate times, the first gate time is 125us, uses queue0, the second gate time is 125us, uses queue6, the third gate time is 250us, uses queue0.

One stream named flow1 uses queue6 to send.

The tx routine repeats send stream flow1 at 1 second intervals,  the rx routine receives stream flow1, we can get the rx time stamp of each stream flow1.

We get a cycle start time by using  ((rx time stamp)/cycle time  * cycle time), then we get the gate start time and gate end time of stream flow1.

We compare the rx time stamp with gate end time, if  (gate start time) < (rx time stamp) <  (gate end time), we  think the stream was send correctly in the gate time.

By the way, because the tda4vh connect to ls1028 directly, the link delay is about 700ns, so we just think the send time is the time of  rx time stamp.

Then from here, you  can see our test based on the 1588 function. We take tda4vh as a slave and ls1028 as a master.

In our test, we need to make slave clock synchronize with master clock firstly. Here is the 1588 clock synchronization log.(because i can post a picture, just copy part of information)

# Timestamp, State, Clock ID, One Way Delay, Offset From Master, Slave to Master, Master to Slave, Observed Drift, Last packet Received
1970-01-01 00:05:18.203442469, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000010, 0.000000666, 0.000000734, -22841.209625097, D
1970-01-01 00:05:19.203463126, slv, 00049ffffe05f721()/01, 0.000000736, 0.000000010, 0.000000661, 0.000000759, -22838.365441694, D
1970-01-01 00:05:20.203486863, slv, 00049ffffe05f721()/01, 0.000000736, 0.000000015, 0.000000678, 0.000000744, -22834.099088329, D
1970-01-01 00:05:21.203509121, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000001, 0.000000678, 0.000000725, -22834.383517052, S
1970-01-01 00:05:22.203532107, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000008, 0.000000691, 0.000000729, -22836.658844042, D
1970-01-01 00:05:23.203554529, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000009, 0.000000693, 0.000000723, -22839.218633322, D
1970-01-01 00:05:24.203576603, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000011, 0.000000693, 0.000000726, -22842.347320934, S
1970-01-01 00:05:25.203599431, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000008, 0.000000693, 0.000000729, -22844.622770701, S
1970-01-01 00:05:26.203623157, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000011, 0.000000680, 0.000000720, -22847.751374909, D
1970-01-01 00:05:27.203645092, slv, 00049ffffe05f721()/01, 0.000000736, -0.000000007, 0.000000680, 0.000000739, -22849.742340308, S
1970-01-01 00:05:28.203667021, slv, 00049ffffe05f721()/01, 0.000000735, 0.000000007, 0.000000657, 0.000000748, -22847.751339710, S
1970-01-01 00:05:29.203691796, slv, 00049ffffe05f721()/01, 0.000000735, 0.000000017, 0.000000657, 0.000000757, -22842.916265061, S
1970-01-01 00:05:30.203713714, slv, 00049ffffe05f721()/01, 0.000000735, 0.000000018, 0.000000660, 0.000000750, -22837.796684022, S
1970-01-01 00:05:31.203743831, slv, 00049ffffe05f721()/01, 0.000000735, 0.000000008, 0.000000690, 0.000000738, -22835.521274831, S
1970-01-01 00:05:32.203759558, slv, 00049ffffe05f721()/01, 0.000000735, -0.000000011, 0.000000702, 0.000000711, -22838.649826670, D
1970-01-01 00:05:33.203784225, slv, 00049ffffe05f721()/01, 0.000000735, -0.000000024, 0.000000702, 0.000000710, -22845.475877131, S
1970-01-01 00:05:34.203805235, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000014, 0.000000682, 0.000000730, -22849.457808899, S
1970-01-01 00:05:35.203828166, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000008, 0.000000682, 0.000000755, -22847.182516874, S
1970-01-01 00:05:36.203850384, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000022, 0.000000661, 0.000000759, -22840.925355571, S
1970-01-01 00:05:37.203876811, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000015, 0.000000660, 0.000000741, -22836.659035996, S
1970-01-01 00:05:38.203896864, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000015, 0.000000660, 0.000000741, -22836.659035996, S
1970-01-01 00:05:39.203920637, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000000, 0.000000679, 0.000000727, -22836.659035996, S
1970-01-01 00:05:40.203943318, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000004, 0.000000682, 0.000000731, -22837.796692504, D
1970-01-01 00:05:41.203965460, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000001, 0.000000682, 0.000000738, -22837.512273542, S
1970-01-01 00:05:42.203989109, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000001, 0.000000691, 0.000000731, -22837.227849775, S
1970-01-01 00:05:43.204010939, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000005, 0.000000688, 0.000000725, -22838.649909185, D
1970-01-01 00:05:44.204034782, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000009, 0.000000688, 0.000000724, -22841.209659261, S
1970-01-01 00:05:45.204056721, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000005, 0.000000691, 0.000000733, -22842.631766408, S
1970-01-01 00:05:46.204081424, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000009, 0.000000691, 0.000000715, -22845.191471941, S
1970-01-01 00:05:47.204102498, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000010, 0.000000682, 0.000000732, -22848.035616288, D
1970-01-01 00:05:48.204124725, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000004, 0.000000682, 0.000000727, -22849.173292881, S
1970-01-01 00:05:49.204148403, slv, 00049ffffe05f721()/01, 0.000000734, -0.000000004, 0.000000679, 0.000000731, -22850.310923038, D
1970-01-01 00:05:50.204170607, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000003, 0.000000679, 0.000000742, -22849.457686305, S
1970-01-01 00:05:51.204193615, slv, 00049ffffe05f721()/01, 0.000000734, 0.000000001, 0.000000685, 0.000000728, -22849.173283705, S

When the value of offset from master reaches a small value , in this log it’s less than 20ns, we think slave clock has synchronized with master. 

After that, set GCL configure to hardware, tda4vh sends stream  flow1 at 1 second interval, ls1028 receives the stream, here is log information of receiver:

-> Hello, World! sequence: 0 ;Gate Start TIME 380:167625000; Rx TIME 380:167715661; Rx Offset: 90661 ns; OK
Hello, World! sequence: 1 ;Gate Start TIME 381:155125000; Rx TIME 381:155238241; Rx Offset: 113241 ns; OK
Hello, World! sequence: 2 ;Gate Start TIME 382:155125000; Rx TIME 382:155261116; Rx Offset: 136116 ns; MISS
Hello, World! sequence: 3 ;Gate Start TIME 383:155125000; Rx TIME 383:155283991; Rx Offset: 158991 ns; MISS
Hello, World! sequence: 4 ;Gate Start TIME 384:155125000; Rx TIME 384:155306861; Rx Offset: 181861 ns; MISS
Hello, World! sequence: 5 ;Gate Start TIME 385:155125000; Rx TIME 385:155329741; Rx Offset: 204741 ns; MISS
Hello, World! sequence: 6 ;Gate Start TIME 386:155125000; Rx TIME 386:155352616; Rx Offset: 227616 ns; MISS
Hello, World! sequence: 7 ;Gate Start TIME 387:155125000; Rx TIME 387:155375501; Rx Offset: 250501 ns; MISS
Hello, World! sequence: 8 ;Gate Start TIME 388:155125000; Rx TIME 388:155398386; Rx Offset: 273386 ns; MISS
Hello, World! sequence: 9 ;Gate Start TIME 389:155125000; Rx TIME 389:155421261; Rx Offset: 296261 ns; MISS
Hello, World! sequence: 10 ;Gate Start TIME 390:155125000; Rx TIME 390:155444141; Rx Offset: 319141 ns; MISS
Hello, World! sequence: 11 ;Gate Start TIME 391:155125000; Rx TIME 391:155467026; Rx Offset: 342026 ns; MISS
Hello, World! sequence: 12 ;Gate Start TIME 392:155125000; Rx TIME 392:155489901; Rx Offset: 364901 ns; MISS
Hello, World! sequence: 13 ;Gate Start TIME 393:155625000; Rx TIME 393:155512781; Rx Offset: 4294855077 ns; OK
Hello, World! sequence: 14 ;Gate Start TIME 394:155625000; Rx TIME 394:155535666; Rx Offset: 4294877962 ns; OK
Hello, World! sequence: 15 ;Gate Start TIME 395:155625000; Rx TIME 395:155558556; Rx Offset: 4294900852 ns; OK
Hello, World! sequence: 16 ;Gate Start TIME 396:155625000; Rx TIME 396:155581446; Rx Offset: 4294923742 ns; OK
Hello, World! sequence: 17 ;Gate Start TIME 397:155625000; Rx TIME 397:155604326; Rx Offset: 4294946622 ns; OK
Hello, World! sequence: 18 ;Gate Start TIME 398:155625000; Rx TIME 398:155627211; Rx Offset: 2211 ns; OK
Hello, World! sequence: 19 ;Gate Start TIME 399:155625000; Rx TIME 399:155650101; Rx Offset: 25101 ns; OK
Hello, World! sequence: 20 ;Gate Start TIME 400:155625000; Rx TIME 400:155672991; Rx Offset: 47991 ns; OK
Hello, World! sequence: 21 ;Gate Start TIME 401:155625000; Rx TIME 401:155695881; Rx Offset: 70881 ns; OK
Hello, World! sequence: 22 ;Gate Start TIME 402:155625000; Rx TIME 402:155718771; Rx Offset: 93771 ns; OK
Hello, World! sequence: 23 ;Gate Start TIME 403:155625000; Rx TIME 403:155741651; Rx Offset: 116651 ns; OK
Hello, World! sequence: 24 ;Gate Start TIME 404:155625000; Rx TIME 404:155764536; Rx Offset: 139536 ns; MISS
Hello, World! sequence: 25 ;Gate Start TIME 405:155625000; Rx TIME 405:155787431; Rx Offset: 162431 ns; MISS
Hello, World! sequence: 26 ;Gate Start TIME 406:155625000; Rx TIME 406:155810321; Rx Offset: 185321 ns; MISS
Hello, World! sequence: 27 ;Gate Start TIME 407:155625000; Rx TIME 407:155833216; Rx Offset: 208216 ns; MISS
Hello, World! sequence: 28 ;Gate Start TIME 408:155625000; Rx TIME 408:155856111; Rx Offset: 231111 ns; MISS
Hello, World! sequence: 29 ;Gate Start TIME 409:155625000; Rx TIME 409:155879011; Rx Offset: 254011 ns; MISS
Hello, World! sequence: 30 ;Gate Start TIME 410:155625000; Rx TIME 410:155901916; Rx Offset: 276916 ns; MISS
Hello, World! sequence: 31 ;Gate Start TIME 411:155625000; Rx TIME 411:155924816; Rx Offset: 299816 ns; MISS
Hello, World! sequence: 32 ;Gate Start TIME 412:155625000; Rx TIME 412:155947721; Rx Offset: 322721 ns; MISS
Hello, World! sequence: 33 ;Gate Start TIME 413:155625000; Rx TIME 413:155970621; Rx Offset: 345621 ns; MISS
Hello, World! sequence: 34 ;Gate Start TIME 414:155625000; Rx TIME 414:155993526; Rx Offset: 368526 ns; MISS
Hello, World! sequence: 35 ;Gate Start TIME 415:156125000; Rx TIME 415:156016421; Rx Offset: 4294858717 ns; OK
Hello, World! sequence: 36 ;Gate Start TIME 416:156125000; Rx TIME 416:156039316; Rx Offset: 4294881612 ns; OK
Hello, World! sequence: 37 ;Gate Start TIME 417:156125000; Rx TIME 417:156062216; Rx Offset: 4294904512 ns; OK
Hello, World! sequence: 38 ;Gate Start TIME 418:156125000; Rx TIME 418:156085116; Rx Offset: 4294927412 ns; OK
Hello, World! sequence: 39 ;Gate Start TIME 419:156125000; Rx TIME 419:156108021; Rx Offset: 4294950317 ns; OK

From this log, Rx TIME is the rx timestamp of stream. As I said before,  I use Rx TIME to calculate  a cycle start time, and then use gate time to calculate the stream gate start time and gate end time.

Rx offset = Rx TIME – Gate Start TIME,  if Rx TIME < Gate End TIME, It’s OK, otherwise  MISS.

In this log, I listed 39 streams I receives, it contains three scenarios:

First, 0 < Rx offset < gate time(125us), description is OK,  this means the stream flow1 was sent in the period of the right gate time in the current cycle.

Second, Rx offset > gate time(125us),  description is MISS, this means the stream flow1 was sent in the period of the next gate time in the current cycle.

Third, Rx offset is a negative value, just like 4294858717, that is Gate Start TIME is greater than Rx TIME, this means the stream was sent in the period of the previous gate time of next cycle.

The phenomenon of second and third is strange, it shouldn’t happen in theory. Let review the GCL configure again.

The cycle Time is 500us, each cycle splits into three gate times, the first gate time is 125us,  uses queue0, the second gate time is 125us, uses queue6, the third gate time is 250us, uses queue0.

One stream named flow1 uses queue6 to send.  The tx routine repeats send stream flow1 at 1 second intervals, if the GCL work normal, the stream is sent only at the second gate time of a cycle.

However, from my test result, the stream can be sent at any gate time of a cycle.

Then, I changed tda4vh as a master and ls1028 as a slave,  with same configure, tested again, here is log information of receiver:

-> Hello, World! sequence: 0 ;Gate Start TIME 332:459125000; Rx TIME 332:459126176; Rx Offset: 1176 ns; OK
Hello, World! sequence: 1 ;Gate Start TIME 333:458125000; Rx TIME 333:458126176; Rx Offset: 1176 ns; OK
Hello, World! sequence: 2 ;Gate Start TIME 334:458125000; Rx TIME 334:458126171; Rx Offset: 1171 ns; OK
Hello, World! sequence: 3 ;Gate Start TIME 335:458125000; Rx TIME 335:458126176; Rx Offset: 1176 ns; OK
Hello, World! sequence: 4 ;Gate Start TIME 336:458125000; Rx TIME 336:458126166; Rx Offset: 1166 ns; OK
Hello, World! sequence: 5 ;Gate Start TIME 337:458125000; Rx TIME 337:458126181; Rx Offset: 1181 ns; OK
Hello, World! sequence: 6 ;Gate Start TIME 338:458125000; Rx TIME 338:458126186; Rx Offset: 1186 ns; OK
Hello, World! sequence: 7 ;Gate Start TIME 339:458125000; Rx TIME 339:458126181; Rx Offset: 1181 ns; OK
Hello, World! sequence: 8 ;Gate Start TIME 340:458125000; Rx TIME 340:458126181; Rx Offset: 1181 ns; OK
Hello, World! sequence: 9 ;Gate Start TIME 341:458125000; Rx TIME 341:458126171; Rx Offset: 1171 ns; OK
Hello, World! sequence: 10 ;Gate Start TIME 342:458125000; Rx TIME 342:458126166; Rx Offset: 1166 ns; OK
Hello, World! sequence: 11 ;Gate Start TIME 343:458125000; Rx TIME 343:458126171; Rx Offset: 1171 ns; OK
Hello, World! sequence: 12 ;Gate Start TIME 344:458125000; Rx TIME 344:458126171; Rx Offset: 1171 ns; OK
Hello, World! sequence: 13 ;Gate Start TIME 345:458125000; Rx TIME 345:458126181; Rx Offset: 1181 ns; OK
Hello, World! sequence: 14 ;Gate Start TIME 346:458125000; Rx TIME 346:458126176; Rx Offset: 1176 ns; OK
Hello, World! sequence: 15 ;Gate Start TIME 347:458125000; Rx TIME 347:458126186; Rx Offset: 1186 ns; OK
Hello, World! sequence: 16 ;Gate Start TIME 348:458125000; Rx TIME 348:458126186; Rx Offset: 1186 ns; OK
Hello, World! sequence: 17 ;Gate Start TIME 349:458125000; Rx TIME 349:458126176; Rx Offset: 1176 ns; OK
Hello, World! sequence: 18 ;Gate Start TIME 350:458125000; Rx TIME 350:458126166; Rx Offset: 1166 ns; OK
Hello, World! sequence: 19 ;Gate Start TIME 351:458125000; Rx TIME 351:458126171; Rx Offset: 1171 ns; OK
Hello, World! sequence: 20 ;Gate Start TIME 352:458125000; Rx TIME 352:458126166; Rx Offset: 1166 ns; OK
Hello, World! sequence: 21 ;Gate Start TIME 353:458125000; Rx TIME 353:458126171; Rx Offset: 1171 ns; OK
Hello, World! sequence: 22 ;Gate Start TIME 354:458125000; Rx TIME 354:458126176; Rx Offset: 1176 ns; OK
Hello, World! sequence: 23 ;Gate Start TIME 355:458125000; Rx TIME 355:458126176; Rx Offset: 1176 ns; OK

This log shows a pretty good result, the stream was sent at a fixed period of gate time in a cycle, the sending time is not shifted to the next gate time or the previous gate time.

So I think the GCL works normally.

That is all my test procedures and results.

Questions: Testing  EST based on 1588 function, when taking tda4vh as a slave, GCL cannot work well, one stream can be sent at any gate time.

The phenomenon is the send time always shift backwards. With streams sending, the sending time shifts from the current gate time to the next gate time in a cycle ,then shifts to

the previous gate time of next cycle.

My  analysis: For EST , it changes gate time to fetch count based on speed,  then write commands which consist of 14-bit fetch count and b-bit tc mask() to fetch ram of each port.

The 22-bit fetch command will be applied for the fetch count in wireside clocks. When enable ESTF, at start of each cycle time, it will schedule the port command and know the gate time

and tc mask, then know a stream be sent with a specific queue and correct time period. However, as a slave ,it needs to keep up with master and make a adjustment.

So whether the gate time or cycle time changes when schedule the fetch command or not,  the GCL didn’t work the way we thought it would.

I’m not sure I understand the EST function correctly, and I guess your test is different with us. I need your professional knowledge and advice to solve this problem.

First, I want to know if you have tested EST function when taking tda4vh as a slave. If not, please try it and see if it has the same problem.

If done and didn’t find the same problem ,please help me analyze it and give me some advice to solve it. Thank you very much in advance.

 

Looking forward to your reply.

 

Thanks,

Caishuang

  • Hello Caishuang,

    If I understand correctly, you mean to say that in the setup with
    TDA4VH as Master clock and ls1028 as Slave clock, the results
    are good, but with TDA4VH as Slave clock and ls1028 as Master
    clock, the results are bad. Additionally, in both the cases, TDA4VH
    is the sender and EST is scheduled on TDA4VH. If that's the case,
    then it appears to me that while the PHC on TDA4VH is synchronizing
    to the clock on ls1028, the system time on TDA4VH is not being matched
    with the PHC on TDA4VH. By PHC, I am referring to the PTP Hardware Clock.

    In Linux, we use the phc2sys command to synchronize the System time
    with the PHC. Please check if there is an equivalent for VxWorks which
    will synchronize the PHC to the System time and retest with TDA4VH as
    Slave clock and ls1028 as Master clock.

    Regards,
    Siddharth.

  • Hi Siddharth

     

    Thanks for your reply. Unfortunately,  synchronize the System time with the PHC is not the root cause. My Problem is that fetch commands are not executed accurately

     

    I noticed that EST function uses two kinds of clocks, They are  CPTS_RFT_CLK and wire clock.

     

    1.CPTS_RFT_CLK

     

    The datasheet describes that the EST function generator generates the EST time interval as a configured number of CPTS reference clocks (CPTS_RFT_CLK) and the EST function generator rising edge is the cycle start time and the cycle repeats (cycle start occurs) after every time interval.

     

    That means the cycle time and start time of  transmission Gate Control List are based on CPTS_RFT_CLK.

    However, when TDA4VH as a slave device, the ptp clock(CPTS_RFT_CLK) needs to make adjustment and keep up with the master device. I wonder if this operation affect the start time or cycle time of EST.

     

    PTP slave will adjust frequency by setting CPTS_CONTROL_REG, CPTS_TS_PPM_LOW_VAL_REG, CPTS_TS_PPM_HIGH_VAL_REG

     

    ESTF also has CPTS_TS_ESTF_CONTROL_REG, CPTS_TS_ESTF_PPM_LOW_VAL_REG, CPTS_TS_ESTF_PPM_HIGH_VAL_REG, but their value are set to zero when enable ESTF. When do I set these registers and why?

     

    1. wire clock

     What’s a wire clock?

     

    The datasheet describes that Each 22-bit fetch command consists of a 14-bit fetch count (14 MSB’s) and an 8-bit priority fetch allow (8 LSB’s) that will be applied for the fetch count time in wireside clocks.

    So the wire clcoks refer to the tx clock of cpsw port? or others?

    My problem is that fetch command are not executed accurately, I want a queue to send packets only at its own interval,  but now a queue not only send packets at its own interval time, but also other interval times?
    Could you give me more information about the wire clock? How does it make sure fetch command executed accurately.

     

    other questions: Is there any relationship between ptp clock(CPTS_RFT_CLK) and wire clock?  Does PTP clock affect wire clock when tda4vh as a slave? Should I make adjustment for wire clock?

     

    Looking forward to your reply, thank you in advance.

     

    Best Regards,

    Caishuang

  • Hello Caishuang,

    Please refer to the following commit in Linux which to me appears to be addressing the issue you are observing:
    https://github.com/torvalds/linux/commit/7849c42da2ca09f11fe04aeb8dbde63df756edaa

    Regards,
    Siddharth.