Performance measurement for Interfaces to DSP Peripherals

Memory performance depends on many factors: the memory design (speed, topology, layout), the type of application, the condition of the cache vs. how the code is written, what else is happening during the memory transfers (like interrupts) and the software layers the application is built upon. We assume you already know what you mean by "performance" and thus the kind of tests that you want to run.

A quick and dirty test is to use the C6452 EVM and CCS. Connect to the board and run the GEL script which initializes the EMIF and DDR. You can then write very short mem copy type of programs to test mem transfer rates.

For bare metal (no OS) type of thruput tests, you can download the Board Support Library that comes with the C6452 EVM, or Chip Support Library (CSL). It is low-level C code that can help with initialization of the EMIFA and DDRC. The links are on the product web site.

If you are using DSP/BIOS it is available with CCS. Again create a task that performs mem copies to measure speeds and other tasks and interrupts to simulate your run-time condition.

To compare with raw throutput refer to document SPRAAZ9 "TMS320DM648/7 SoC Architecture and Throughput Overview" table 5 for DDR2 and EMIF data. The DM648 has similar interface to C6452 DSP.

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Hi,

Thanks for the information.

As i know the idle factors for different peripherals of the DSP. But what i want to do is i try to measure the performance if i write some block of data in FPGA or DDR2

in my setup how it is working in our environment. As i have no evaluation board, i am doing the measurements directly on the target. So what i want to do now is just to create one task and try to perform mem copies to measure the speeds. But my question is if some other tasks are running in the mean time, how accurate are these measurements? is this a suitable way to do these speed measurements?

Thanks,

Regards,

Ramana.

The EVM code is generic enough to be modidied for your target set up and memory map. IMHO an "accurate" assessment of memory bandwidth performance depends on whether the measured condition applies to the actual worst case "run-time" condition for your equipment. The type of transfer also matter, e.g. is the block aligned so that the maximum bus width and most efficient code is used.

If you writing under DSP/BIOS, check out CCS RTA capabilities. This tool which is part of CCS gives you visibility in terms of what task, SWI are running under the DSPBIOS during run-time.

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Ramana,

I don't use DSP/BIOS, so I can't comment on ways of using that for performance measurements.

But I will tell you one method I have used, that works well.

I configure one or more I/O pins as GPIO lines, and watch them with a logic analyzer.  Then I add code before and after the loop to be measured, where that code  sets or clear the GPIO pin.  The timing analysis in the logic analyzer tells me the execution time of the loop.

Steve Tuttle