This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM625: LPDDR4 configuration and operating temperature

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I'm using "DDR subsystem register configuration" (https://dev.ti.com/sysconfig) to output the dtsi used by u-boot to configure the DDRSS.

The help, near to "Operating Temperature Range", says:

"Set the operating temperature range. Note that the refresh rate (tREFIab and tREFIpb) need to be decreased if operating above 85C (see DDR datasheet). Parameters tDQSCK, tRCD, tRC, tRAS, tRP, tRRD will automatically be derated above 85C"

If I understand well neither u-boot nor linux change any configuration at runtime and, additionally, I expect that temperature sensor register (MR4) of LPDDR4 memory is automatically read out by DDRSS.

The question is: is tREFI automatically changed by the controller (if I understand well all LPDDR4 have similar behaviour about tREFI/temperature), should we change it in some way or should we configure the "optimal" value valid for all temperatures?

Another question: when I change the Operating Temperature Range in sysconfig some values in the configuration are changing in the dtsi file but not in the sysconfig page. How these register are changing?

Thank you.

Best regards

  • I think currently, the SDK does not have support for dynamically changing the refresh rate based on temp.  I believe this is scheduled to be added in a future release.  So you will have to set the refresh rate based on the max temperature you plan to operate. 

    So, for example, if you plan to operate all the way to 125C, change the Operating Temperature Range to -40C to 125C.  This also automatically de-rates some of the appropriate parameters (you can see these in the DDR datasheet)  (this answers your last question)

    You will also have to make the following changes manually in the tool

    tREFIab = 975ns

    tREFIpb = 122ns

    tRASmax = 8775ns

    tDQSCKmax = 3.6ns

    Note that the next release of the DDR register configuration tool (post v9.08) will make these changes automatically when you change Operating Temperature Range.  Once the SDK support dynamic changes, the config tool will change accordingly.

    Regards,

    James

  • Thank you James for the quick reply,

    all clear.

    Best regards.

    Emanuele