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AM3352: Refresh Rate Settings for DRAM controller

Kenley
Intellectual 1755 points
Part Number: AM3352

Hi Team,

My customer have 3 questions about refresh rate settings for DRAM controller of AM3352.

1. The current setting is reg_refresh_rate=0x0C30(DEC 3120) and tREFI=3120/(400MHz)=7.8us for 400MHz CLK (without SSC). Is it Okay or not ?
→I think this setting depends on the DRAM parameter, should I ask them to check the parameter of their DRAM ?

2. If there is a conflict between the DRAM refresh command and another command (write, read, etc.), it is assumed that the refresh interval will be extended for the conflicting command, is my understanding correct ?

3. Does the AM3352 have the function to avoid such situations, or control so the tREF of each cell does not exceed 64ms even if the refresh interval is extended?

Thank you in advance.

Best regards,

Kenley

  • +1
    TI__Guru* 85990 points

    1.  The refresh rate is set based on the DDR specification.  For DDR3 at nominal temperatures, refreshes need to occur at 7.8us intervals (see the DDR datasheet for this value).  That is the reason for the setting of 3120 when the operating frequency is 400MHz

    2.  Yes, the DDR controller will manage any conflicts between sending a refresh command and any other command.  It will ensure refreshes are sent at the appropriate interval

    3.  There is no software control for this.  The DDR controller will manage the refreshes based on the reg_refresh_rate value.  

    Regards,

    James

  • 0 in reply to JJD
    TI__Intellectual 1755 points

    Hi James,

    Thank you! 

    Kenley

  • 0 in reply to JJD
    TI__Intellectual 1755 points

    Hi James,
    My customer has additional questions about DRAM refresh scheduling.
    1. Could you tell me what are the possible cases when the refresh command is not executed?
    Because the refresh mode should be designed with the highest priority, so it is hard to understand why the refresh command will not be executed and the refresh backlog counter will be incremented.

    2. Related to question no.1, what will happen if the refresh is not executed within 64 ms due to conflict with another command ?

    Thanks and best regards,

    Kenley

  • 0 in reply to Kenley
    TI__Guru* 85990 points

    Kenley, the DDR controller will handle arbitration of the refresh command.  This is explained in section 7.3.3.5.5 of the TRM.  The controller will issue the refresh commands only when necessary to avoid affecting performance.  This is all handled by the controller.  

    Regards,

    James

  • 0 in reply to JJD
    TI__Intellectual 1755 points

    Hi James,

    Thank you for your prompt reply.


    Yes, that's what customer is worried about because the controller will issue the refresh commands only when necessary. Just in case that the refresh is not fully executed within 64 ms due to the the conflict with another command. 
    Even though the urgency level turns to "Refresh Must", it will stop refreshing after it turns to "Refresh Release" which means that there are remaining refresh commands that are not executed. From the above reason, there is a possibility that all the refresh command could not be executed and might exceed 64ms.

    Thanks and best regards,

    Kenley

  • 0 in reply to Kenley
    TI__Guru* 85990 points

    But it still won't violate any refresh requirements of the memory.  The JEDEC standard allows flexibility in the spacing of refresh operations, and allows you to defer up to 8 refreshes as long as the controller eventually catches up and provides the required amount of refreshes over the refresh period.  This timing is guaranteed from the controller

    Regards,

    James