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OMAP3 BT656 no ISP interrupts

Other Parts Discussed in Thread: AM3715

Greetings,

I'm working with custom hardware that has an OMAP3 connected to a BT656 sensor with DATA[0:7] and PCLK connected from the sensor to the OMAP3.  I'm working with the OMAP ISP driver from the 2.6.32 based PSP and have my board-support file configured as such:

 

 static struct isp_interface_config bt656_if_config = {

        .ccdc_par_ser       = ISP_PARLL_YUV_BT,

        .dataline_shift     = 0x0,      /* no shifting of d[0:10] */

        .strobe             = 0x0,

        .prestrobe          = 0x0,

        .shutter            = 0x0,

        .wait_hs_vs         = 2,

        .u.par.par_bridge   = 0x0,      /* bridge not enabled */

        .u.par.par_clk_pol  = 0x1,      /* inverted - latch data on falling edge */

};

I've verified the following is happening in the ISP driver:
- ispccdc_config_sync_if getting called with syncif:
                syncif.ccdc_mastermode = 0;
                syncif.datapol = 0;
                syncif.datsz = DAT8;
                syncif.fldmode = 1;
                syncif.fldout = 0;
                syncif.fldpol = 0;
                syncif.fldstat = 0;
                syncif.hdpol = 0;
                syncif.ipmod = YUV8;
                syncif.vdpol = 0;
                syncif.bt_r656_en = 1;
- ISPCCDC_SYN_MODE - ISPCCDC_SYN_MODE_DATSIZ_8, ISPCCDC_SYN_MODE_INPMOD_YCBCR8,  ISPCCDC_SYN_MODE_PACK8 are set
- ISPCCDC_REC656IF  - ISPCCDC_REC656IF_R656ON is set
- ISP_IRQ0ENABLE - the following are set - IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
                | IRQ0ENABLE_HS_VS_IRQ
                | IRQ0ENABLE_CCDC_VD0_IRQ | IRQ0ENABLE_CCDC_VD1_IRQ
                | IRQ0ENABLE_CSIA_IRQ
                | IRQ0ENABLE_CSIB_IRQ
                | IRQ0ENABLE_H3A_AWB_DONE_IRQ | IRQ0ENABLE_H3A_AF_DONE_IRQ
My understanding is that VD0/VD1 interrupts should be enabled in my case where there is no external HS/VS input to the OMAP3 ISP.   From reading the TRM it seems that when in BT656 mode that SAV/EAV should be decoded from the datastream and responsible for asserting VD0/VD1 interrupts.   I can't see exactly where this is specified (that SAV/EAV trigger VD0/VD1 interrupts) in the TRM however because it speaks of VD0/VD1 as always derived from HS/VS signals.
Am I missing something here?
Thanks,
Tim