TDA4VM: CPSW9G port mapping to SERDES0 in QSGMII mode

John Weber

Part Number: TDA4VM

Based on the TRM for the TDA4VM, the CPSW9G (CPSW0) maps each port to a specific serdes and serdes lane.

In the QP-ENET expansion, when it is connected to the J7-EVM with TDA4VM, it connects to serdes 0, lane 1. This is called SGMII 2, which makes sense because it is connected to port 2 of CPSW0.

Based on other conversations with TI applications engineering, we understand that when using QSGMII, the specific port used (in this case CPSW0 port 2) and a selection of higher-numbered ports can be part of the QSGMII link. So, in this case ports 2-5. Or ports 2,4,5, and 6 (for example).

What we understand is the port 1 cannot participate in the QSGMII link. If we wanted to have port 1 in the QSGMII link, then we would have to connect a QSGMII PHY to Serdes0, lane 0. Can you please confirm or clarify this?

over 2 years ago

0 ShreyasRao over 2 years ago

TI__Guru 62050 points

Hi John,

I know that the QSGMII will use 4 ports of SGMII onto one serdes lane. I will confirm which ports it would use.

0 ShreyasRao over 2 years ago in reply to ShreyasRao

TI__Guru 62050 points

It’s intended to be flexible. If Port2 is the QSGMII port then 1,3,4 can be QSGMII_SUB ports (or any ports).

The lowest 3 QSGMII_SUB ports will be combined with the first QSGMII port.

0 John Weber over 2 years ago in reply to ShreyasRao

Intellectual 511 points

Thanks Shreyas!

It seems like this is the case for the TDA4VM EVM with the QP ENET expansion card, showing the ports configured as QSGMII_MAIN and QSGMII_SUB:

In the kernel source, it is clear how serdes 0 lane 1 is configured as QSGMII:

git.ti.com/.../k3-j721e-evm-quad-port-eth-exp.dtso

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes0 {
	status = "okay";

	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
	#address-cells = <1>;
	#size-cells = <0>;

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz0 2>;
	};
};

In the native Linux Ethernet driver, how are the QSGMII_SUB ports designated?

Finally, is the following design also possible?

In this design, Serdes 0, lane 0 (SGMII1) is designated as QSGMII_MAIN, while ports 2,3, and 4 are designated as QSGMII_SUB and would be grouped into the SGMII1 interface.

Thanks!

John

0 John Weber over 2 years ago in reply to John Weber

Intellectual 511 points

I think I found it in the kernel documentation, but would like confirmation.

Relevant document:

Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml:

ti,qsgmii-main-ports:
 $ref: /schemas/types.yaml#/definitions/uint32-array
 description: |
 Required only for QSGMII mode. Array to select the port for
 QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
 ports automatically. For J7200 CPSW5G with the compatible:
 ti,j7200-cpsw5g-phy-gmii-sel, ti,qsgmii-main-ports is an
 array of only one element, which is the port number ranging
 from 1 to 4. For J721E CPSW9G with the compatible:
 ti,j721e-cpsw9g-phy-gmii-sel, and
 For J784S4 CPSW9G with the compatible:
 ti,j784s4-cpsw9g-phy-gmii-sel, ti,qsgmii-main-ports is an
 array of two elements, which corresponds to two pairs of
 4 ports each. The first element and second element of the
 array both range from 1 to 4 each. However, for the second
 element, the values 1 to 4 map to the ports 5 to 8. Thus,
 it is possible to specify which port among the two different
 sets of 4 ports is the QSGMII main port. For example:
 ti,qsgmii-main-ports = <2>, <1>;
 would mean that of the 8 CPSW9G ports, ports 2 and 5 are the
 main ports for the two sets of QSGMII interfaces formend by
 ports 1-4 and ports 5-8. Both elements need to be filled
 if the property is being used. For example, if the first set of
 4 ports are configured for RGMII and the second set of 4 ports
 are configured for QSGMII with port 7 being the main port, then:
 ti,qsgmii-main-ports = <1>, <3>;
 is the correct value for this configuration. It does not matter
 what the first element's value is, but a valid value must be
 filled even if any of the first 4 ports are not being used in
 QSGMII mode.

In arch/arm64/boot/dts/ti/k3-j721e-main.dtsi, ports 2 and 5 are set to QSGMII_MAIN:

 cpsw0_phy_gmii_sel: phy@4044 {
 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
 ti,qsgmii-main-ports = <2>, <1>;
 reg = <0x4044 0x20>;
 #phy-cells = <1>;
 };

If we wished to use CPSW9G port 1 and port 5 as QSGMII, it would mean a change to the following:

 cpsw0_phy_gmii_sel: phy@4044 {
 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
 ti,qsgmii-main-ports = <1>, <1>;
 reg = <0x4044 0x20>;
 #phy-cells = <1>;
};

0 ShreyasRao over 2 years ago in reply to John Weber

TI__Guru 62050 points

Hi John,

Yes, SERDES0 Lane0 configured as QSGMII is possible.

0 John Weber over 2 years ago in reply to ShreyasRao

Intellectual 511 points

If we were to use SERDES0 Lane 0 as QSGMII, is the following the right way to configure the DTS?

 cpsw0_phy_gmii_sel: phy@4044 {
 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
 ti,qsgmii-main-ports = <1>, <1>;
 reg = <0x4044 0x20>;
 #phy-cells = <1>;
};

0 ShreyasRao over 2 years ago in reply to John Weber

TI__Guru 62050 points

Hi John,

I believe that your config is right for S0L0 usage. I will loop in s/w app experts to comment as well.

0 Doredla Sudheer Kumar over 2 years ago in reply to ShreyasRao

TI__Guru 63920 points

Hi,

cpsw0_phy_gmii_sel: phy@4044 {
compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
ti,qsgmii-main-ports = <1>, <1>;
reg = <0x4044 0x20>;
#phy-cells = <1>;
};Above is configuring the Port-1 and Port-5 as main ports of QSGMII.

John Weber said:
If we were to use SERDES0 Lane 0 as QSGMII, is the following the right way to configure the DTS?

Yes, your configuration is correct.

But, by default Native Linux driver is not enabled in SDK offering. So, port configuration will be on Ethfw.

If you want to enable Native Linux Driver, Please follow FAQ [How to Move to Native Linux Driver] and update port configuration as required in overlays.

If you want to go with Ethfw based default solution, Please refer to EthFw User Gide for more details.
For modification of Port configuration, please refer to Porting Guide.

Best Regards,
Sudheer

0 John Weber over 2 years ago in reply to Doredla Sudheer Kumar

Intellectual 511 points

Thanks Sudheer, for confirming the port configuration.

We already have the native Linux driver working, but appreciate your advice and information.

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TDA4VM: CPSW9G port mapping to SERDES0 in QSGMII mode